coreboot-gerrit January 2022

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Change in coreboot[master]: nb/intel/{sandybridge,haswell}: Rename PCIe driver
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60600 ) Change subject: nb/intel/{sandybridge,haswell}: Rename PCIe driver ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/sandybridge/pcie.c: https://review.coreboot.org/c/coreboot/+/60600/comment/777d080a_377e241a PS1, Line 66: sa_pcie Just an idea: How about naming it "nb_pcie"? So it reflects the file path (src/northbridge/intel/...) and we don't use too many names for the same thing. -- To view, visit https://review.coreboot.org/c/coreboot/+/60600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I019088fcaa7866d8002e6884c25e1acd1d149093 Gerrit-Change-Number: 60600 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 Jan 2022 15:10:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/{sandybridge,haswell}: Rename PCIe driver
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60600 ) Change subject: nb/intel/{sandybridge,haswell}: Rename PCIe driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I019088fcaa7866d8002e6884c25e1acd1d149093 Gerrit-Change-Number: 60600 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 Jan 2022 15:06:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Enable building with SecureBoot support
by Sean Rhodes (Code Review) 01 Jan '22

01 Jan '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60636 ) Change subject: payloads/tianocore: Enable building with SecureBoot support ...................................................................... payloads/tianocore: Enable building with SecureBoot support Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I377f06754ff09a2879892bd9e3bd575b56ff1f4e --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/60636/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 072d8d1..ade22b5 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -151,6 +151,7 @@ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ + CONFIG_TIANOCORE_SECUREBOOT=$(CONFIG_TIANOCORE_SECUREBOOT) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index b7069aa..ad6533a 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -112,6 +112,10 @@ useful for bootloaders that are not fully 64-bit aware such as Qubes R4.0.4 bootloader. +config TIANOCORE_SECUREBOOT + bool "Enable Secureboot Support" + default y + endif if TIANOCORE_COREBOOTPAYLOAD diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index a4ccfc7..5479587 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -46,6 +46,10 @@ 4G=-D ABOVE_4G_MEMORY=FALSE endif +ifeq ($(CONFIG_TIANOCORE_SECUREBOOT),y) +SB=-D SECURE_BOOT_ENABLE=TRUE +endif + TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) @@ -55,7 +59,7 @@ ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE else -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) +BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) $(SB) endif all: clean build -- To view, visit https://review.coreboot.org/c/coreboot/+/60636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I377f06754ff09a2879892bd9e3bd575b56ff1f4e Gerrit-Change-Number: 60636 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_device.c: Don't guard `pci_dev_disable_bus_master()`
by Felix Singer (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60599 ) Change subject: pci_device.c: Don't guard `pci_dev_disable_bus_master()` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813e0f72c3c624c73ab9ecbe7512359608ace927 Gerrit-Change-Number: 60599 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 01 Jan 2022 15:05:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Remove unused <string.h>
by Felix Held (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, HAOUAS Elyes. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60558 ) Change subject: soc/amd: Remove unused <string.h> ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3e7a62a2e833017f550eddd915b7dfb539d019 Gerrit-Change-Number: 60558 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 01 Jan 2022 15:00:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Use 'stdint.h' when appropriate
by Felix Held (Code Review) 01 Jan '22

01 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60549 ) Change subject: src: Use 'stdint.h' when appropriate ...................................................................... src: Use 'stdint.h' when appropriate Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/hp/folio_9480m/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/msi/h81m-p33/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/gm45/early_init.c M src/soc/intel/baytrail/include/soc/modphy_table.h M src/soc/intel/baytrail/modphy_table.c M src/southbridge/intel/i82801gx/early_init.c 11 files changed, 2 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 75efb9e..25b157d 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index cc9a04f..3573d69 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index a818d87..ecf5490 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c index f1df3ef..fa7cba1 100644 --- a/src/mainboard/hp/folio_9480m/romstage.c +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 07a0083..936703b 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c index 5a8f479..f4db2644 100644 --- a/src/mainboard/msi/h81m-p33/romstage.c +++ b/src/mainboard/msi/h81m-p33/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index f7711c0..01dab69 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 6e3ea2c..e911064 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <device/pci_ops.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" diff --git a/src/soc/intel/baytrail/include/soc/modphy_table.h b/src/soc/intel/baytrail/include/soc/modphy_table.h index 9a483c4..0561841 100644 --- a/src/soc/intel/baytrail/include/soc/modphy_table.h +++ b/src/soc/intel/baytrail/include/soc/modphy_table.h @@ -3,6 +3,8 @@ #ifndef _BAYTRAIL_MODPHY_TABLE_H_ #define _BAYTRAIL_MODPHY_TABLE_H_ +#include <stdint.h> + struct modphy_entry { u8 port; u32 reg; diff --git a/src/soc/intel/baytrail/modphy_table.c b/src/soc/intel/baytrail/modphy_table.c index f028c8f..ebda700 100644 --- a/src/soc/intel/baytrail/modphy_table.c +++ b/src/soc/intel/baytrail/modphy_table.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <soc/modphy_table.h> struct modphy_entry reva0_modphy_table[] = { /* SOC stepping A0/A1 */ diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index c8a6117..4647bf1 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <console/console.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Gerrit-Change-Number: 60549 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: console: Create helper function to get max console log level
by Subrata Banik (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60470 ) Change subject: console: Create helper function to get max console log level ...................................................................... Patch Set 3: (1 comment) File src/console/init.c: https://review.coreboot.org/c/coreboot/+/60470/comment/536f7df7_78c2f9ec PS2, Line 55: return get_log_level(); > > Initially I had the same understanding as well but later I realised that `get_log_level()` will re […] Thanks, will wait for Nico's reply on this thought. -- To view, visit https://review.coreboot.org/c/coreboot/+/60470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397 Gerrit-Change-Number: 60470 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Jan 2022 14:56:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove duplicated includes
by Felix Held (Code Review) 01 Jan '22

01 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60438 ) Change subject: src: Remove duplicated includes ...................................................................... src: Remove duplicated includes Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/brya/bootblock.c M src/mainboard/google/guybrush/variants/guybrush/gpio.c M src/mainboard/google/guybrush/variants/nipperkin/gpio.c M src/mainboard/google/herobrine/mainboard.c M src/soc/amd/picasso/fsp_s_params.c M src/soc/intel/broadwell/pch/adsp.c 6 files changed, 0 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index ac0dc32..d391cd1 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <fmap.h> #include <commonlib/region.h> -#include <console/console.h> #include <cpu/intel/cpu_ids.h> #include <intelblocks/pmclib.h> #include <cf9_reset.h> diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 0ebee22..cea1f42 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -5,7 +5,6 @@ #include <boardid.h> #include <gpio.h> #include <soc/gpio.h> -#include <baseboard/variants.h> /* This table is used by guybrush variant with board version < 2. */ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index df55e52..0b3b9b2 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -5,7 +5,6 @@ #include <boardid.h> #include <gpio.h> #include <soc/gpio.h> -#include <baseboard/variants.h> /* This table is used by nipperkin variant with board version < 2. */ static const struct soc_amd_gpio bid1_override_gpio_table[] = { diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index a2e0786..fcc468e 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -3,11 +3,9 @@ #include "board.h" #include <boardid.h> #include <bootblock_common.h> -#include <soc/clock.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> -#include <bootblock_common.h> #include <soc/clock.h> #include <soc/qupv3_config_common.h> #include <soc/qup_se_handlers_common.h> diff --git a/src/soc/amd/picasso/fsp_s_params.c b/src/soc/amd/picasso/fsp_s_params.c index 57e51d5..af7de37 100644 --- a/src/soc/amd/picasso/fsp_s_params.c +++ b/src/soc/amd/picasso/fsp_s_params.c @@ -9,7 +9,6 @@ #include <soc/soc_util.h> #include <fsp/api.h> #include "chip.h" -#include <device/pci.h> static void fsps_update_emmc_config(FSP_S_CONFIG *scfg, const struct soc_amd_picasso_config *cfg) diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c index eaae08b..e154446 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/soc/intel/broadwell/pch/adsp.c @@ -9,7 +9,6 @@ #include <device/mmio.h> #include <soc/adsp.h> #include <soc/device_nvs.h> -#include <soc/device_nvs.h> #include <soc/pch.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Gerrit-Change-Number: 60438 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Drop duplicated includes
by Felix Held (Code Review) 01 Jan '22

01 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60437 ) Change subject: src: Drop duplicated includes ...................................................................... src: Drop duplicated includes <types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/acpi/gnvs.c M src/arch/x86/include/arch/cpu.h M src/drivers/tpm/ppi.c M src/drivers/tpm/ppi_stub.c M src/include/thread.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/intel/adlrvp/board_id.c M src/mainboard/starlabs/labtop/smbios.c M src/northbridge/intel/x4x/dq_dqs.c M src/security/intel/txt/logging.c M src/soc/amd/common/block/include/amdblocks/acp.h M src/soc/amd/common/block/lpc/spi_dma.c M src/soc/intel/alderlake/elog.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/meminit.h M src/soc/intel/jasperlake/elog.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/mediatek/common/flash_controller.c M src/soc/mediatek/common/include/soc/dpm.h M src/soc/mediatek/mt8192/include/soc/spm.h M src/soc/mediatek/mt8195/include/soc/spm.h M src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h 24 files changed, 0 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 8024783..6de345f 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <console/console.h> #include <soc/nvs.h> -#include <stdint.h> #include <string.h> #include <types.h> diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 9a3b63d..d3f50bf 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -3,7 +3,6 @@ #ifndef ARCH_CPU_H #define ARCH_CPU_H -#include <stdint.h> #include <types.h> /* diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c index 88dd649..6b02d45 100644 --- a/src/drivers/tpm/ppi.c +++ b/src/drivers/tpm/ppi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <stddef.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <acpi/acpi_device.h> diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c index 1e3a7fc..23236ff 100644 --- a/src/drivers/tpm/ppi_stub.c +++ b/src/drivers/tpm/ppi_stub.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> -#include <stddef.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <acpi/acpi_device.h> diff --git a/src/include/thread.h b/src/include/thread.h index 4f10782..f414db0 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -4,7 +4,6 @@ #include <arch/cpu.h> #include <bootstate.h> -#include <commonlib/bsd/cb_err.h> #include <types.h> struct thread_mutex { diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 9785a3a..e1765fa 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -8,7 +8,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/ioapic.h> -#include <stdint.h> #include <device/device.h> #include <stdlib.h> #include <string.h> diff --git a/src/mainboard/intel/adlrvp/board_id.c b/src/mainboard/intel/adlrvp/board_id.c index 332ba1b..de7a380 100644 --- a/src/mainboard/intel/adlrvp/board_id.c +++ b/src/mainboard/intel/adlrvp/board_id.c @@ -3,7 +3,6 @@ #include <boardid.h> #include <ec/acpi/ec.h> #include <ec/google/chromeec/ec.h> -#include <stdint.h> #include <types.h> #include "board_id.h" diff --git a/src/mainboard/starlabs/labtop/smbios.c b/src/mainboard/starlabs/labtop/smbios.c index 8babae3..9acf64f 100644 --- a/src/mainboard/starlabs/labtop/smbios.c +++ b/src/mainboard/starlabs/labtop/smbios.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <ec/starlabs/merlin/ec.h> -#include <limits.h> #include <option.h> #include <smbios.h> #include <types.h> diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index e4cc888..870e660 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <stdint.h> #include <string.h> #include <types.h> #include "raminit.h" diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index f3e37aa..46c594c 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -3,7 +3,6 @@ #include <arch/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <stdint.h> #include <types.h> #include "txt.h" diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h index a4c926d..13254e4 100644 --- a/src/soc/amd/common/block/include/amdblocks/acp.h +++ b/src/soc/amd/common/block/include/amdblocks/acp.h @@ -3,7 +3,6 @@ #ifndef AMD_COMMON_ACP_H #define AMD_COMMON_ACP_H -#include <stdint.h> #include <types.h> struct acp_config { diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index baf1eb8..2c183ee 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -4,7 +4,6 @@ #include <amdblocks/spi.h> #include <assert.h> #include <boot_device.h> -#include <commonlib/bsd/cb_err.h> #include <commonlib/bsd/helpers.h> #include <commonlib/region.h> #include <console/console.h> diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 7b0fd87..7f79d94 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -8,7 +8,6 @@ #include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <stdint.h> #include <types.h> struct pme_map { diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 49e3c76..debdef2 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -3,8 +3,6 @@ #ifndef _SOC_ALDERLAKE_MEMINIT_H_ #define _SOC_ALDERLAKE_MEMINIT_H_ -#include <stddef.h> -#include <stdint.h> #include <types.h> #include <fsp/soc_binding.h> #include <intelblocks/meminit.h> diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index a80ab48..05b67ee 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -11,7 +11,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/cse.h> -#include <limits.h> #include <option.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> diff --git a/src/soc/intel/common/block/include/intelblocks/meminit.h b/src/soc/intel/common/block/include/intelblocks/meminit.h index cbec04d..1fed02f 100644 --- a/src/soc/intel/common/block/include/intelblocks/meminit.h +++ b/src/soc/intel/common/block/include/intelblocks/meminit.h @@ -3,8 +3,6 @@ #ifndef __SOC_INTEL_COMMON_BLOCK_MEMINIT_H__ #define __SOC_INTEL_COMMON_BLOCK_MEMINIT_H__ -#include <stddef.h> -#include <stdint.h> #include <types.h> /* diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 61b8fb8..0e4b2c5 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -8,7 +8,6 @@ #include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <stdint.h> #include <types.h> struct pme_map { diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 93174be..301c88a 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -8,7 +8,6 @@ #include <intelblocks/xhci.h> #include <soc/pci_devs.h> #include <soc/pm.h> -#include <stdint.h> #include <types.h> struct pme_map { diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 8583e66..6b3086c 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -3,8 +3,6 @@ #ifndef _SOC_TIGERLAKE_MEMINIT_H_ #define _SOC_TIGERLAKE_MEMINIT_H_ -#include <stddef.h> -#include <stdint.h> #include <types.h> #include <fsp/soc_binding.h> #include <intelblocks/meminit.h> diff --git a/src/soc/mediatek/common/flash_controller.c b/src/soc/mediatek/common/flash_controller.c index cdda056..3fe17f8 100644 --- a/src/soc/mediatek/common/flash_controller.c +++ b/src/soc/mediatek/common/flash_controller.c @@ -7,7 +7,6 @@ #include <soc/symbols.h> #include <spi_flash.h> #include <spi-generic.h> -#include <stdint.h> #include <string.h> #include <symbols.h> #include <timer.h> diff --git a/src/soc/mediatek/common/include/soc/dpm.h b/src/soc/mediatek/common/include/soc/dpm.h index 8c110aa..e72b6a1 100644 --- a/src/soc/mediatek/common/include/soc/dpm.h +++ b/src/soc/mediatek/common/include/soc/dpm.h @@ -5,7 +5,6 @@ #include <soc/addressmap.h> #include <soc/mcu_common.h> -#include <stdint.h> #include <types.h> struct dpm_regs { diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index d99ca65..4951f13 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -5,7 +5,6 @@ #include <soc/addressmap.h> #include <soc/mtcmos.h> -#include <stdint.h> #include <types.h> /* SPM READ/WRITE CFG */ diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index fb7d17f..945852a 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -6,7 +6,6 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/mtcmos.h> -#include <stdint.h> #include <types.h> /* SPM READ/WRITE CFG */ diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h index 57a3022..112cac6 100644 --- a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h +++ b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h @@ -4,7 +4,6 @@ #define _SOC_DISPLAY_MDSS_REG_H_ #include <types.h> -#include <stdint.h> struct dsi_regs { uint32_t hw_version; -- To view, visit https://review.coreboot.org/c/coreboot/+/60437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Gerrit-Change-Number: 60437 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
by Subrata Banik (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Andrey Petrov, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Andrey Petrov, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60402 to look at the new patch set (#7). Change subject: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional ...................................................................... drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional The FSP API is used to notify the FSP about different phases in the boot process. The current FSP specification support three notify phases: - Post PCI enumeration - Ready to Boot - End of Firmware This patch attempts to make FSP Notify Phase APIs optional by using native coreboot implementation to perform the required lock down and chipset register configuration prior boot to payload. BUG=b:211954778 TEST=Able to build brya without any compilation issue and coreboot log with this code changes when SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT and SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config enabled. coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/notify.c 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/60402/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/60402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95e9ec25ae797f2ac8e1c74145cf21e59867d64 Gerrit-Change-Number: 60402 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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