coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

1 participants
6716 discussions

Change in coreboot[master]: soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`
by Tim Wawrzynczak (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Felix Singer, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60026 ) Change subject: soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()` ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e79f637bedec0bdca1312291328b2385bd027a7 Gerrit-Change-Number: 60026 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 Jan 2022 22:09:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/mainboard/google: Remove unused <acpi/acpi.h>
by Tim Wawrzynczak (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Nick Vaccaro, HAOUAS Elyes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60623 ) Change subject: src/mainboard/google: Remove unused <acpi/acpi.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fc65c5e01bb134e2e3068dc6da03de1183f785 Gerrit-Change-Number: 60623 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 01 Jan 2022 22:05:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent
by Tim Wawrzynczak (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Felix Singer, Subrata Banik, Paul Menzel, Angel Pons, Arthur Heymans, Nick Vaccaro, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60441 ) Change subject: soc/intel/alderlake: Add option to make MRC log silent ...................................................................... Patch Set 7: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60441/comment/e50a5f3b_c0b7b39b PS7, Line 9: aka nit: `AKA` https://review.coreboot.org/c/coreboot/+/60441/comment/afbcc03c_48b38229 PS7, Line 22: aka `AKA` -- To view, visit https://review.coreboot.org/c/coreboot/+/60441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Gerrit-Change-Number: 60441 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 01 Jan 2022 22:04:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/fsp: Map FSP debug level to coreboot console level
by Tim Wawrzynczak (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons, Andrey Petrov, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60471 ) Change subject: drivers/intel/fsp: Map FSP debug level to coreboot console level ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/60471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Gerrit-Change-Number: 60471 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Jan 2022 22:02:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: console: Make get_log_level a public function
by Angel Pons (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Nico Huber, Subrata Banik, Tim Wawrzynczak, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60470 ) Change subject: console: Make get_log_level a public function ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60470/comment/7eb74df2_f8d588a8 PS4, Line 10: rather nit: rather *than* File src/include/console/console.h: https://review.coreboot.org/c/coreboot/+/60470/comment/2ed45e3f_1217add7 PS4, Line 66: 0 0 is BIOS_EMERG, should we return `-1` instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/60470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397 Gerrit-Change-Number: 60470 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Jan 2022 21:51:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
by Angel Pons (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Felix Singer, Wonkyu Kim, Michał Żygowski, Ravishankar Sarawadi, Stefan Reinauer, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56171 ) Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs ...................................................................... Patch Set 4: (2 comments) File util/inteltool/gpio_names/tigerlake.h: PS4: > I don't think this would be copyrightable/licensable anyway I think the other headers were split off some C file in the past. I'd just put the same license header on these, just to have one. Then again, I'm not a lawyer 😄 https://review.coreboot.org/c/coreboot/+/56171/comment/e2c79b62_c8577387 PS4, Line 300: /* : * GPP_A group does not start right after GPP_T group and GPP_T group does not : * start right after GPP_B. Fill the holes with Reserved on both sides. : */ > Yep. I'd stumbled upon that, too. […] Interesting -- To view, visit https://review.coreboot.org/c/coreboot/+/56171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6071a999be9e8a372997db0369218f297e579d08 Gerrit-Change-Number: 56171 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Sat, 01 Jan 2022 21:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Angel Pons (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Arthur Heymans, Felix Singer, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 ) Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/60405/comment/6184c8d7_d6339436 PS7, Line 279: HeciEnabled > > Ah, the HECI device can be enabled and initialised in coreboot, but hidden before booting an OS. So, if I understand correctly, there are multiple cases: > > Yes, you can assume that HECI is default enabled and you can't disable the HECI in the regular operational mode. The only possibility is to make it function disable prior booting to the OS. > > > > > 1. HECI device disabled: I think this happens when CSE is in an abnormal state (e.g. because of some error or because it has been disabled). This situation should be detected at runtime and dealt with accordingly. > > Yes, Mostly like EOP failure scenarios. > > > > > 2. HECI device enabled, and left visible: This is the simplest thing to do when the CSE is running normally, but I'm not sure if there are any drawbacks. I know Windows Device Manager shows a "yellow bang" for the HECI device when its drivers aren't installed, but it's not a serious problem. > > You've correctly pointed out. When you don't have a HECI driver installed then ideally it's like Yellow bang or in linux, it tries to bind a generic PCI driver. There was an issue reported starting with SKL or KBL (I forgot the platform name) where the system was unable to enter into S0ix due to HECI. The debug data we had at that time was pointing to any access to HECI device PCI configuration space causing the non-entering to S0ix issue. Later we had to find a way to make HECI function disable when we don't have a driver in Chrome OS. This was the case mostly till CML, hence, you may find most of the Chrome platform prior to TGL had HeciEnabled set to `0` and post TGL it's set to `1` . Now I don't think we need to use `HeciEnabled` for any platform going forward. Interesting, I wasn't aware of the S0ix problems. > > > > 3. HECI device enabled, but hidden before booting an OS: I think this is to avoid the Windows Device Manager "yellow bang" thing when the drivers aren't installed, and I think it also saves a bit of power by keeping the HECI device in D0i3. Other than that, I'm not sure if there are any other reasons to do this. > > Yes, I have mentioned the issue in detail, why we had to come up with HeciEnabled config variable. > > > > > Case 1 would be handled as part of the CSE error handling flows, so we don't need to worry about it in this commit. Cases 2 and 3 are with CSE running normally. This makes me wonder: are there any reasons to prefer case 2 over case 3, or viceversa? If so, which ones? > > I hope now you have context as well, reading the issue descriptor above. Yes, thank you very much! > > > > If there's no (mainboard-specific) reason for a particular mainboard to require either case 2 or case 3, I was thinking of having a user-configurable Kconfig option to control hiding the HECI device. This still allows mainboards to override the default setting, and also allows non-mainboard code to do so. For instance, if Chrome OS needs case 3, one would only need to override the default once with `if CHROMEOS` or similar. > > I think we can take a few actions as below based on our discussion > 1. Retire HeciEnabled from all SOC and MB. Sounds good. > 2. Replace the functionality that HeciEnable was achieving with DT CSE PCI device on/off. Typically this can manage Case #2 above. I'd prefer to keep the PCI device enabled in the devicetree. This way, we can use regular device operations instead of bootstate hooks. Yes, this means the HECI device will always be enabled in the devicetree. We can hide the HECI devices using the `.final` operation. > 3. SoC code to make CSE hidden (almost case #3 above) when both DT CSE PCI device is off and the user selects HECI_DISABLE_USING_SMM config.This can also provide flexibility in the hand of mb user to choose if they wish to pick between case #2 or #3. The user can't control HECI_DISABLE_USING_SMM, it doesn't have a prompt. This is why I was thinking of adding a new Kconfig option to replace the functionality of `HeciEnabled`. > WDYT? > > > > > Thoughts? I suppose Tim is on vacation. I'd like to know his thoughts as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 01 Jan 2022 21:46:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: payloads/tianocore: Change default branch to uefipayload_202201
by Sean Rhodes (Code Review) 01 Jan '22

01 Jan '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60644 ) Change subject: payloads/tianocore: Change default branch to uefipayload_202201 ...................................................................... payloads/tianocore: Change default branch to uefipayload_202201 Change default EDKII branch to uefipayload_202201 which inludes the following changes: * Add support for TPM * Add secureboot support * Allow changing the boot menu key * Rebase on upstream Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I7fee7e5414ea01a6049be6c1b9b7abc3776cc7d0 --- M payloads/external/tianocore/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/60644/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 9c79de9..aeafcf4 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -6,7 +6,7 @@ project_name=Tianocore project_dir=$(CURDIR)/tianocore project_git_repo=https://github.com/mrchromebox/edk2 -project_git_branch=uefipayload_202107 +project_git_branch=uefipayload_202201 upstream_git_repo=https://github.com/tianocore/edk2 build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/60644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fee7e5414ea01a6049be6c1b9b7abc3776cc7d0 Gerrit-Change-Number: 60644 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: payloads/tianocore: Add option to change Boot Menu key
by Sean Rhodes (Code Review) 01 Jan '22

01 Jan '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60643 ) Change subject: payloads/tianocore: Add option to change Boot Menu key ...................................................................... payloads/tianocore: Add option to change Boot Menu key The coreboot version of Tianocore maps Escape to the boot menu. This is problematic for many Linux distributions that use GRUB, as this also maps Escape to access it's menu. This option can be used to specific an F-Key to replace Escape Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I41df3e15aa73be41fb9836fe6e202319b02a3ffb --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/60643/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index ade22b5..f6eb85e 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -149,6 +149,7 @@ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ + CONFIG_TIANOCORE_BOOT_MENU_F_KEY=$(CONFIG_TIANOCORE_BOOT_MENU_F_KEY) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ CONFIG_TIANOCORE_SECUREBOOT=$(CONFIG_TIANOCORE_SECUREBOOT) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index ad6533a..f160400 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -116,6 +116,14 @@ bool "Enable Secureboot Support" default y +config TIANOCORE_BOOT_MENU_F_KEY + string "Function key for boot menu" + help + The coreboot version of Tianocore maps Escape to the boot menu. + This is problematic for many Linux distributions that use GRUB, + as this also maps Escape to access it's menu. This option can + be used to specific an F-Key to replace Escape. + endif if TIANOCORE_COREBOOTPAYLOAD diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index a26a0e8..9c79de9 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -55,6 +55,10 @@ TPM=-D TPM_ENABLE=TRUE endif +ifneq ($(CONFIG_TIANOCORE_BOOT_MENU_F_KEY),) +BOOT_MENU_KEY=-D BOOT_MENU_KEY=$(CONFIG_TIANOCORE_BOOT_MENU_F_KEY) +endif + TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) -- To view, visit https://review.coreboot.org/c/coreboot/+/60643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41df3e15aa73be41fb9836fe6e202319b02a3ffb Gerrit-Change-Number: 60643 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/starlabs/merlin: Apply EC settings when suspending
by Sean Rhodes (Code Review) 01 Jan '22

01 Jan '22

Attention is currently required from: Andy Pont. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60165 ) Change subject: ec/starlabs/merlin: Apply EC settings when suspending ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/60165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf Gerrit-Change-Number: 60165 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Comment-Date: Sat, 01 Jan 2022 21:28:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2022