coreboot-gerrit January 2022

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Change in coreboot[master]: sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Patrick Rudolph. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60667 ) Change subject: sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/i82801ix/acpi/ich9.asl M src/southbridge/intel/i82801ix/acpi/lpc.asl 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/60667/1 diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 1a07ec2..5722b4c 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -173,7 +173,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl index b97b010..72e28eb 100644 --- a/src/southbridge/intel/i82801ix/acpi/lpc.asl +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -72,15 +72,15 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { + If (HPAS == 1) { HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { + If (HPAS == 2) { HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { + If (HPAS == 3) { HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/60667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Gerrit-Change-Number: 60667 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60666 ) Change subject: sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/i82801jx/acpi/ich10.asl M src/southbridge/intel/i82801jx/acpi/lpc.asl 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/60666/1 diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index 0e4c03b..2324696 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -175,7 +175,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index b97b010..72e28eb 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -72,15 +72,15 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { + If (HPAS == 1) { HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { + If (HPAS == 2) { HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { + If (HPAS == 3) { HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/60666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Gerrit-Change-Number: 60666 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60665 ) Change subject: soc/intel/apollolake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... soc/intel/apollolake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I55297104c17b71a4d7cc28e2da91598f746c0073 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/acpi/pch_hda.asl M src/soc/intel/apollolake/acpi/pcie_port.asl M src/soc/intel/apollolake/acpi/scs.asl 4 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/60665/1 diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 6791e15..768bebb 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -99,7 +99,7 @@ GLEN = GMAX - GMIN + 1 /* Patch PM02 range based on Memory Size */ - If (LEqual (A4GS, 0)) { + If (A4GS == 0) { CreateQwordField (MCRS, PM02._LEN, MSEN) Store (0, MSEN) } Else { diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl index 6c9a14a..5739dff 100644 --- a/src/soc/intel/apollolake/acpi/pch_hda.asl +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -29,17 +29,17 @@ * Arg2 - Function Index */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LEqual (Arg1, One) && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) { + If (Arg1 == 1 && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) { Return (Buffer (One) { 0x03 }) } Else { @@ -54,7 +54,7 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl index 34e2a73..cfdb6de 100644 --- a/src/soc/intel/apollolake/acpi/pcie_port.asl +++ b/src/soc/intel/apollolake/acpi/pcie_port.asl @@ -40,7 +40,7 @@ Method (_STA, 0, Serialized) { Store (PDS, PDST) - If (LEqual (PDS, 1)) { + If (PDS == 1) { Return (0xf) } Else { Return (0) @@ -49,7 +49,7 @@ Method (_ON, 0, Serialized) { - If (LEqual (PDST, 1) && LNotEqual (\PRT0, 0)) { + If (PDST == 1 && LNotEqual (\PRT0, 0)) { /* Enter this condition if device * is connected */ @@ -83,7 +83,7 @@ Method (_OFF, 0, Serialized) { /* Set L23_Rdy Entry Request (L23ER) */ - If (LEqual (PDST, 1) && LNotEqual (\PRT0, 0)) { + If (PDST == 1 && LNotEqual (\PRT0, 0)) { /* enter this condition if device * is connected */ diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index a5a1f06..840cfbe 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -23,9 +23,9 @@ */ Method (SCPG, 2, Serialized) { - if (LEqual(Arg0, 0x1)) { + if (Arg0 == 1) { Or (^GENR, Arg1, ^GENR) - } ElseIf (LEqual(Arg0, 0x0)){ + } ElseIf (Arg0 == 0) { And (^GENR, Arg1, ^GENR) } } @@ -44,13 +44,13 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 9: Device Readiness Durations * Returns a package of five integers covering * various device related delays in PCIe Base Spec. */ - If (LEqual (Arg2, 9)) { + If (Arg2 == 9) { /* * Function 9 support for revision 3. * ECN link for function definitions @@ -58,7 +58,7 @@ * specification_documents/ * ECN_fw_latency_optimization_final.pdf] */ - If (LEqual (Arg1, 3)) { + If (Arg1 == 3) { /* * Integer 0: FW reset time. * Integer 1: FW data link up time. @@ -143,7 +143,7 @@ * If sdcard is not present, rxstate is High. * Write the inverted value of rxstate to GRR3. */ - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Store (1, ^^GRR3) } Else { Store (0, ^^GRR3) -- To view, visit https://review.coreboot.org/c/coreboot/+/60665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55297104c17b71a4d7cc28e2da91598f746c0073 Gerrit-Change-Number: 60665 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Patrick Rudolph. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60664 ) Change subject: soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... soc/intel/cannonlake/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I844d5d2fdf0a84171385054cf7c7ca222d73c0fc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/acpi/pch_hda.asl M src/soc/intel/cannonlake/acpi/scs.asl 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/60664/1 diff --git a/src/soc/intel/cannonlake/acpi/pch_hda.asl b/src/soc/intel/cannonlake/acpi/pch_hda.asl index db2d664..85182f9 100644 --- a/src/soc/intel/cannonlake/acpi/pch_hda.asl +++ b/src/soc/intel/cannonlake/acpi/pch_hda.asl @@ -26,17 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LEqual (Arg1, One) && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) { + If (Arg1 == 1 && LNotEqual (NHLA, Zero) && LNotEqual (NHLL, Zero)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -50,7 +50,7 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 462e65a..4c01b48 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -73,7 +73,7 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^DSUU)) { + If (Arg0 == ^DSUU) { /* Check the revision */ If (LGreaterEqual (Arg1, Zero)) { /* @@ -92,8 +92,8 @@ * Bit 6 - Indicates support for HS400 mode * Bit 9 - Indicates eMMC I/O Driver Strength */ - If (LEqual (Arg2, Zero)) { - If (Lequal (VDID, 0x02c48086) ) { + If (Arg2 == 0) { + If (VDID == 0x02c48086) { /* * Set bit 9 for CML eMMC to indicate * eMMC I/O driver strength is supported @@ -111,7 +111,7 @@ * 3 - 100 ohm * 4 - 40 ohm */ - If (LEqual (Arg2, 9)) { + If (Arg2 == 9) { Return(Buffer() {0x4}) } } @@ -146,7 +146,7 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^DSUU)) { + If (Arg0 == ^DSUU) { /* Check the revision */ If (LGreaterEqual (Arg1, Zero)) { /* @@ -165,7 +165,7 @@ * For SD we have to support functions to * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { Return (Buffer () { 0x19 }) } /* @@ -175,7 +175,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - If (LEqual (Arg2, 3)) { + If (Arg2 == 3) { Sleep (100) Return(Buffer () { 0x00 }) } @@ -186,7 +186,7 @@ * UHS SD card on PCH. This is to compensate * for the SD VR slowness. */ - If (LEqual (Arg2, 4)) { + If (Arg2 == 4) { Sleep (100) Return(Buffer () { 0x00 }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/60664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I844d5d2fdf0a84171385054cf7c7ca222d73c0fc Gerrit-Change-Number: 60664 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/quanta/it8518/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60663 ) Change subject: ec/quanta/it8518/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... ec/quanta/it8518/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I6732fd876524feab924a58434bec381dcdb87bce Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/quanta/it8518/acpi/battery.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/60663/1 diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 48c8e35..98f6775 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -63,12 +63,12 @@ Method (WAEC) { Store (20, Local0) // Timeout 100 msec - While (LEqual (HSID, Zero)) + While (HSID == 0) { // EC Is not ready Sleep (5) Local0-- - If (LEqual (Local0, Zero)) + If (Local0 == 0) { Break } @@ -233,7 +233,7 @@ } // Set critical flag if battery is empty - If (LEqual (And (HB0S, 0x0F), 0)) + If (And (HB0S, 0x0F) == 0) { Or (Local0, 4, Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/60663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6732fd876524feab924a58434bec381dcdb87bce Gerrit-Change-Number: 60663 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Tim Wawrzynczak. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60662 ) Change subject: ec/google/chromeec/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... ec/google/chromeec/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I4d79080ecfe457766983b20a0217ccadcd188fcf Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/google/chromeec/acpi/battery.asl M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/acpi/keyboard_backlight.asl M src/ec/google/chromeec/acpi/tbmc.asl 4 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/60662/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index c28c78a..8b1128f 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -11,7 +11,7 @@ Method (BTSW, 1) { #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE - If (LEqual (BTIX, Arg0)) { + If (BTIX == Arg0) { Return (Zero) } If (LGreaterEqual (Arg0, BTCN)) { @@ -23,7 +23,7 @@ { Sleep (1) Local0-- - If (LEqual (Local0, Zero)) + If (Local0 == 0) { Return (One) } @@ -182,7 +182,7 @@ // Notify if battery state has changed since last time If (LNotEqual (Local1, DeRefOf (Arg2))) { Store (Local1, Arg2) - If (LEqual(Arg0, 0)) { + If (Arg0 == 0) { Notify (BAT0, 0x80) } #ifdef EC_ENABLE_SECOND_BATTERY_DEVICE diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 49e7efc..35e0e00 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -178,22 +178,22 @@ Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0) /* Check for sensor not calibrated */ - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (Zero) } /* Check for sensor not present */ - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (Zero) } /* Check for sensor not powered */ - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (Zero) } /* Check for sensor bad reading */ - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (Zero) } @@ -539,7 +539,7 @@ * DDPN = 0 is reserved for backwards compatibility. * If DDPN == 0 use TBMD to load appropriate DPTF table. */ - If (LEqual (^DDPN, 0)) { + If (^DDPN == 0) { Return (^TBMD) } Else { Local0 = ^DDPN - 1 diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl index 2d4a0c5..4c306d5 100644 --- a/src/ec/google/chromeec/acpi/keyboard_backlight.asl +++ b/src/ec/google/chromeec/acpi/keyboard_backlight.asl @@ -23,11 +23,11 @@ /* If query is unsupported, but this code is compiled * in, assume the backlight exists physically. */ - If (LEqual (1, \_SB.PCI0.LPCB.EC0.DFUD)) { + If (\_SB.PCI0.LPCB.EC0.DFUD == 1) { Return (0xf) } /* If EC reports that backlight exists, trust it */ - If (LEqual (1, \_SB.PCI0.LPCB.EC0.KBLE)) { + If (\_SB.PCI0.LPCB.EC0.KBLE == 1) { Return (0xf) } /* Otherwise: no device -> disable */ diff --git a/src/ec/google/chromeec/acpi/tbmc.asl b/src/ec/google/chromeec/acpi/tbmc.asl index 7be50d7..1661296 100644 --- a/src/ec/google/chromeec/acpi/tbmc.asl +++ b/src/ec/google/chromeec/acpi/tbmc.asl @@ -7,7 +7,7 @@ Name (_DDN, "Tablet Motion Control") Method (TBMC) { - If (LEqual (^^RCTM, One)) { + If (^^RCTM == 1) { Return (0x1) } Else { Return (0x0) -- To view, visit https://review.coreboot.org/c/coreboot/+/60662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d79080ecfe457766983b20a0217ccadcd188fcf Gerrit-Change-Number: 60662 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/h8/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Alexander Couzens. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60661 ) Change subject: ec/lenovo/h8/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... ec/lenovo/h8/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I49a7ed2d57124746815478f3ead8a8f7c54d048a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/lenovo/h8/acpi/ec.asl M src/ec/lenovo/h8/acpi/systemstatus.asl M src/ec/lenovo/h8/acpi/thermal.asl 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/60661/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 18463a5..31ddc55 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -64,9 +64,9 @@ Method (_REG, 2, NotSerialized) { /* Wait for ERAM driver loaded */ - if (LEqual(Arg1, One)) { + if (Arg1 == 1) { /* Fill HKEY defaults on first boot */ - if (LEqual(^HKEY.INIT, Zero)) { + if (^HKEY.INIT == 0) { Store (BTEB, ^HKEY.WBDC) Store (WWEB, ^HKEY.WWAN) Store (One, ^HKEY.INIT) diff --git a/src/ec/lenovo/h8/acpi/systemstatus.asl b/src/ec/lenovo/h8/acpi/systemstatus.asl index a5793be..7598154 100644 --- a/src/ec/lenovo/h8/acpi/systemstatus.asl +++ b/src/ec/lenovo/h8/acpi/systemstatus.asl @@ -5,7 +5,7 @@ { Method(_SST, 1, NotSerialized) { - If (LEqual (Arg0, 0)) { + If (Arg0 == 0) { /* Indicator off */ /* power TLED off */ @@ -14,7 +14,7 @@ \_SB.PCI0.LPCB.EC.TLED(0x07) } - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { /* working state */ /* power TLED on */ @@ -23,7 +23,7 @@ \_SB.PCI0.LPCB.EC.TLED(0x07) } - If (LEqual (Arg0, 2)) { + If (Arg0 == 2) { /* waking state */ /* power LED on */ @@ -32,7 +32,7 @@ \_SB.PCI0.LPCB.EC.TLED(0xc7) } - If (LEqual (Arg0, 3)) { + If (Arg0 == 3) { /* sleep state */ /* power TLED pulsing */ diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index d8346a1..8244bbc7 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -73,7 +73,7 @@ Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (!MEB1 && LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128)) { + If (!MEB1 && \_SB.PCI0.LPCB.EC.TMP0 == 128) { Return (C2K(40)) } Store (1, MEB1) @@ -160,7 +160,7 @@ Method(_TMP) { #if defined(EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ - If (!MEB2 && LEqual (\_SB.PCI0.LPCB.EC.TMP1, 128)) { + If (!MEB2 && \_SB.PCI0.LPCB.EC.TMP1 == 128) { Return (C2K(40)) } Store (1, MEB2) -- To view, visit https://review.coreboot.org/c/coreboot/+/60661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49a7ed2d57124746815478f3ead8a8f7c54d048a Gerrit-Change-Number: 60661 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/gma/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60660 ) Change subject: drivers/intel/gma/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... drivers/intel/gma/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I965a0718f6bca1dc27b928bdd9374857f5ea3215 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/drivers/intel/gma/acpi/common.asl M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/60660/1 diff --git a/src/drivers/intel/gma/acpi/common.asl b/src/drivers/intel/gma/acpi/common.asl index 739b91c..860e1a8 100644 --- a/src/drivers/intel/gma/acpi/common.asl +++ b/src/drivers/intel/gma/acpi/common.asl @@ -7,7 +7,7 @@ Method(BRID, 1, NotSerialized) { Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) - If (LEqual (Local0, Ones)) + If (Local0 == Ones) { Return (SizeOf(BRIG) - 1) } diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index 11d8fcd..ec51915 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -42,11 +42,11 @@ */ Method (XBCM, 1, Serialized) { - If (LEqual(ASLS, Zero)) + If (ASLS == 0) { Return (Ones) } - If (LEqual(And(MBOX, 0x4), Zero)) + If (And(MBOX, 0x4) == 0) { Return (Ones) } @@ -60,7 +60,7 @@ /* also set valid bit */ Store (Or (Local1, 0x80000000), BCLP) - If (LEqual(ARDY, Zero)) + If (ARDY == 0) { Return (Ones) } @@ -74,10 +74,10 @@ While (LGreater(Local0, Zero)) { Sleep (1) - If (LEqual (And (ASLC, 0x2), 0)) { + If (And (ASLC, 0x2) == 0) { /* Request has been processed, check status: */ And (ShiftRight (ASLC, 12), 0x3, Local1) - If (LEqual (Local1, 0)) { + If (Local1 == 0) { Return (Zero) } Else { Return (Ones) @@ -144,7 +144,7 @@ Method (XBCM, 1, NotSerialized) { - If (LEqual(^BOX3.XBCM (Arg0), Ones)) + If (^BOX3.XBCM (Arg0) == Ones) { ^LEGA.XBCM (Arg0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/60660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965a0718f6bca1dc27b928bdd9374857f5ea3215 Gerrit-Change-Number: 60660 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Felix Held. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60659 ) Change subject: superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I033f73e6552746c6899e46ee4d619ab47cb3d55b Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/superio/winbond/w83667hg-a/ps2_controller.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/60659/1 diff --git a/src/superio/winbond/w83667hg-a/ps2_controller.asl b/src/superio/winbond/w83667hg-a/ps2_controller.asl index b0a435e..172a63c 100644 --- a/src/superio/winbond/w83667hg-a/ps2_controller.asl +++ b/src/superio/winbond/w83667hg-a/ps2_controller.asl @@ -54,7 +54,7 @@ /* Restore default SuperIO access */ Store(0xAA, SIOI) - if (LEqual(Local0, 0x0)) { + if (Local0 == 0) { /* Mouse function selected */ Return (0xf) } -- To view, visit https://review.coreboot.org/c/coreboot/+/60659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I033f73e6552746c6899e46ee4d619ab47cb3d55b Gerrit-Change-Number: 60659 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
by Felix Singer (Code Review) 02 Jan '22

02 Jan '22

Attention is currently required from: Felix Held. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60658 ) Change subject: superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntax ...................................................................... superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntax Replace `LEqual(a, b)` with `a == b`. Change-Id: I3833a3a341bd64191cc0b811ca80e96a359307a1 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/superio/winbond/w83627hf/acpi/superio.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/60658/1 diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index cc4bb87..cb50fe5 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -493,7 +493,7 @@ If (Local4) { Store(0x04, IOAL) } - If (LEqual (Local0, 0xBC)) + If (Local0 == 0xBC) { Store (0x04, IOLE) } @@ -564,7 +564,7 @@ CreateByteField (Arg0, IO0._LEN, IOLE) CreateWordField (Arg0, IRQX._INT, IRQL) - If (LEqual(IOAL, 4)) { + If (IOAL == 4) { Store(0x0, Local2) } else { Store(0x1, Local2) -- To view, visit https://review.coreboot.org/c/coreboot/+/60658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3833a3a341bd64191cc0b811ca80e96a359307a1 Gerrit-Change-Number: 60658 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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