Attention is currently required from: Felix Singer, Wonkyu Kim, Michał Żygowski, Ravishankar Sarawadi, Stefan Reinauer.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56171 )
Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
......................................................................
Patch Set 4:
(7 comments)
Patchset:
PS4:
> In some cases there are holes between GPP groups in the same community. […]
meh, confirmed. We've seen that on other platforms already, but TGL seems to be special.... I put together all information I have and these are my results:
Range starts come from the PCH ds, ends are calculated (16*pad count-1)
*** marks additional ranges where the pad names come from refcode. These pads are either NC, used internally or hide behind the various undocumented `RSVD` pads.
The offsets in these cases are educated guesses based on end/start of the adjacent ranges, but it turns out they fit perfectly ;)
```
com0
GPP_B0 - GPP_B23 -> 24p -> 0x700-0x87f
GSPI0_CLK_LOOPBK - GSPI1_ -> 2p -> 0x880-0x89f ***
GPP_T0 - GPP_T1 -> 2p -> 0x8a0-0x8bf ***
GPP_T2 - GPP_T3 -> 2p -> 0x8c0-0x8df
GPP_T4 - GPP_T15 -> 12p -> 0x8e0-0x99f ***
GPP_A0 - GPP_A23 -> 24p -> 0x9a0-0xb1f
ESPI_CLK_LOOPBK ... 0xb20- ***
com1
GPP_S0 - GPP_S7 -> 8p -> 0x700-0x77f
GPP_H0 - GPP_H23 -> 24p -> 0x780-0x8ff
GPP_D0 - GPP_D19 -> 20p -> 0x900-0xa3f
GSPI2_CLK_LOOPBK -> 1p -> 0xa40-0xa4f ***
GPP_U0-U3 -> 4p -> 0xa50-0xa8f ***
GPP_U4 - GPP_U5 -> 2p -> 0xa90-0xaaf
GPP_U6 - GPP_U19 -> 14p -> 0xab0-0xbcf ***
GSPI3_CLK_LOOPBK - GSPI6_ -> 4p -> 0xcd0- ***
com2
GPD0 - GPD11 -> 12p -> 0x700-0x7bf
INPUT3VSEL 0x7c0 ***
SLP_LANB 0x7d0 ***
SLP_SUSB 0x7e0 ***
WAKEB 0x7f0 ***
DRAM_RESETB 0x7d0 ***
com4
GPP_C0 - GPP_C23 -> 24p -> 0x700-0x7bf
GPP_F0 - GPP_F23 -> 24p -> 0x880-0x9ff
GPPF_CLK_LOOPBK -> 1p -> 0xa00-0xa0f ***
L_BKLTEN -> 1p -> 0xa10-0xa1f ***
L_BKLTCTL -> 1p -> 0xa20-0xb2f ***
L_VDDEN -> 1p -> 0xa30-0xc3f ***
SYS_PWROK -> 1p -> 0xa40-0xd4f ***
SYS_RESETB -> 1p -> 0xa50-0xe5f ***
MLK_RSTB -> 1p -> 0xa60-0xa6f ***
GPP_E0 - GPP_E23 -> 24p -> 0xa70-0xbef
GPPE_CLK_LOOPBK -> 1p -> 0xbf0-0xbff ***
com5
GPP_R0 - GPP_R7 -> 8p -> 0x700-0x78f
```
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/438b129e_fc779329
PS4, Line 135: };
missing GSPI2_CLK_LOOPBK
https://review.coreboot.org/c/coreboot/+/56171/comment/8a4bbc3d_4a3111f5
PS4, Line 169: };
24 is GPPE_CLK_LOOPBK, "n/a", "THC0_CLK_LOOPBACK"
https://review.coreboot.org/c/coreboot/+/56171/comment/f954fc89_bca2d3d9
PS4, Line 179: const char *const tigerlake_pch_lp_fe_hole_names[] = {
this is the HVMOS group, compare util/inteltool/gpio_names/cannonlake_lp.h or util/inteltool/gpio_names/icelake.h
L_BKLTEN, L_BKLTEN,
L_BKLTCTL, L_BKLTCTL,
L_VDDEN, L_VDDEN,
SYS_PWROK, SYS_PWROK
SYS_RESETB, SYS_RESETB,
MLK_RSTB, MLK_RSTB,
https://review.coreboot.org/c/coreboot/+/56171/comment/357a950f_697401da
PS4, Line 221: };
24 is GPPF_CLK_LOOPBK, "n/a", "THC1_CLK_LOOPBACK"
https://review.coreboot.org/c/coreboot/+/56171/comment/e36413df_438c2c0b
PS4, Line 336: "Reserved",
one too much. GPP_U4 is on offset 5
https://review.coreboot.org/c/coreboot/+/56171/comment/bf299447_1cf90b2e
PS4, Line 361: };
you can add these as well - all with NF1:
INPUT3VSEL
SLP_LANB
SLP_SUSB
WAKEB
DRAM_RESETB
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