coreboot-gerrit January 2022

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Change in coreboot[master]: soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60728 ) Change subject: soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/smihandler.c 3 files changed, 1 insertion(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/60728/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 1b59ef0..1349f69 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -203,9 +203,6 @@ # - PM_CFG.SLP_LAN_MIN_ASST_WDTH register "PchPmPwrCycDur" = "1" # 1s - # Enable HECI - register "HeciEnabled" = "1" - # Set xHCI LFPS period sampling off time, the default is 9ms. register "xhci_lfps_sampling_offtime_ms" = "9" diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 256fa06..f3e7240 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -142,10 +142,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index 2e38b68..18bcda4 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_jasperlake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802 Gerrit-Change-Number: 60728 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60727 to look at the new patch set (#2). Change subject: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/smihandler.c 5 files changed, 1 insertion(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60727/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Gerrit-Change-Number: 60727 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60726 to look at the new patch set (#2). Change subject: soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config ...................................................................... soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config Make use of `DISABLE_CSE_AT_PRE_BOOT` config instead dt CSE device state to perform CSE function disable using `heci_disable()`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I195390b0af0f69bdb085e9ee2a4a8c3e29fd5a67 --- M src/soc/intel/cannonlake/smihandler.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/60726/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195390b0af0f69bdb085e9ee2a4a8c3e29fd5a67 Gerrit-Change-Number: 60726 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60725 to look at the new patch set (#2). Change subject: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy ...................................................................... mb/google/{drallion, hatch. sarien}: Rework CSE dt policy This patch makes dt CSE PCI device `on` by default and Mainboards selects DISABLE_CSE_AT_PRE_BOOT config to make CSE function disable at pre-boot instead of making dt CSE device 'off'. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 7 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60725/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Gerrit-Change-Number: 60725 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Felix Singer, Erik van den Bogaert, Michał Żygowski, Frans Hendriks, Michael Niewöhner, Patrick Rudolph, Piotr Król. Hello Felix Singer, Erik van den Bogaert, Michał Żygowski, Frans Hendriks, Michael Niewöhner, Patrick Rudolph, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60722 to look at the new patch set (#2). Change subject: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards selects DISABLE_CSE_AT_PRE_BOOT config to make CSE function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/Kconfig M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c 32 files changed, 15 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60722/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Gerrit-Change-Number: 60722 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60727 ) Change subject: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/smihandler.c 5 files changed, 1 insertion(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60727/1 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 1800541..0fdc88a 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -12,9 +12,6 @@ register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 228bf60..87b455f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -12,9 +12,6 @@ register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index ca90557..acb9286 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -12,9 +12,6 @@ register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index e18e52d..210e92c 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -226,10 +226,6 @@ uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c index 6637847..e86a770 100644 --- a/src/soc/intel/elkhartlake/smihandler.c +++ b/src/soc/intel/elkhartlake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_elkhartlake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98 Gerrit-Change-Number: 60727 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60726 ) Change subject: soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config ...................................................................... soc/intel/cnl: Replace `dt CSE dev state` by `CSE disable` config Make use of `DISABLE_CSE_AT_PRE_BOOT` config instead dt CSE device state to perform CSE function disable using `heci_disable()`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I195390b0af0f69bdb085e9ee2a4a8c3e29fd5a67 --- M src/soc/intel/cannonlake/smihandler.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/60726/1 diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index a287a7b..6a78559 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -16,10 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - if (!CONFIG(HECI_DISABLE_USING_SMM)) - return; - - if (!is_devfn_enabled(PCH_DEVFN_CSE)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195390b0af0f69bdb085e9ee2a4a8c3e29fd5a67 Gerrit-Change-Number: 60726 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60725 ) Change subject: mb/google/{drallion, hatch. sarien}: Rework CSE dt policy ...................................................................... mb/google/{drallion, hatch. sarien}: Rework CSE dt policy This patch makes dt CSE PCI device `on` by default and Mainboards selects DISABLE_CSE_AT_PRE_BOOT config to make CSE function disable at pre-boot instead of making dt CSE device 'off'. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c --- M src/mainboard/google/drallion/Kconfig M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 7 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/60725/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index b0b0a5c..03142eb 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -26,6 +26,7 @@ config BOARD_GOOGLE_DRALLION select BOARD_GOOGLE_BASEBOARD_DRALLION + select DISABLE_CSE_AT_PRE_BOOT if BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 105eddb..867dd81 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -411,7 +411,7 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 3d04079..aa3b51d 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -29,6 +29,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select BOARD_GOOGLE_HATCH_COMMON + select DISABLE_CSE_AT_PRE_BOOT select SYSTEM_TYPE_LAPTOP config BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index a84eabd..dea590b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -296,7 +296,7 @@ device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 device pci 15.3 on end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 11f7ac0..b16b946 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -26,11 +26,13 @@ config BOARD_GOOGLE_ARCADA select BOARD_GOOGLE_BASEBOARD_SARIEN + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_INTEL_ISH select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_SARIEN select BOARD_GOOGLE_BASEBOARD_SARIEN + select DISABLE_CSE_AT_PRE_BOOT select MAINBOARD_USES_IFD_GBE_REGION select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0bbc25f..7fdd136 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -342,7 +342,7 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index a447240..3437973 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -363,7 +363,7 @@ end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off end # Management Engine Interface 1 + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection -- To view, visit https://review.coreboot.org/c/coreboot/+/60725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd57d2713fe83de5fb93e399734414ca99977d0c Gerrit-Change-Number: 60725 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Alexander Couzens. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60724 ) Change subject: ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax ...................................................................... ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/lenovo/h8/acpi/thinkpad.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/60724/1 diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index ee813c9..3cec50f 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -91,7 +91,7 @@ } Else { - DHKN = DHKN & Not (Local0) + DHKN = DHKN & !Local0 } If (EN) { -- To view, visit https://review.coreboot.org/c/coreboot/+/60724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504 Gerrit-Change-Number: 60724 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/h8/acpi: Replace And() with ASL 2.0 syntax
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Alexander Couzens. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60723 ) Change subject: ec/lenovo/h8/acpi: Replace And() with ASL 2.0 syntax ...................................................................... ec/lenovo/h8/acpi: Replace And() with ASL 2.0 syntax Change-Id: Id600bcb3fad35455adffe11a8105ad2590e83feb Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/ec/lenovo/h8/acpi/thinkpad.asl 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/60723/1 diff --git a/src/ec/lenovo/h8/acpi/thinkpad.asl b/src/ec/lenovo/h8/acpi/thinkpad.asl index 8d412d2..ee813c9 100644 --- a/src/ec/lenovo/h8/acpi/thinkpad.asl +++ b/src/ec/lenovo/h8/acpi/thinkpad.asl @@ -52,7 +52,7 @@ /* Report event */ Method (RHK, 1, NotSerialized) { ShiftLeft (One, Arg0 - 1, Local0) - If (And (EMSK, Local0)) { + If (EMSK & Local0) { Store (Arg0, BTN) Notify (HKEY, 0x80) } @@ -61,7 +61,7 @@ /* Report tablet */ Method (RTAB, 1, NotSerialized) { ShiftLeft (One, Arg0 - 1, Local0) - If (And (ETAB, Local0)) { + If (ETAB & Local0) { Store (Arg0, BTAB) Notify (HKEY, 0x80) } @@ -91,7 +91,7 @@ } Else { - And (DHKN, Not (Local0), DHKN) + DHKN = DHKN & Not (Local0) } If (EN) { @@ -184,9 +184,9 @@ Store (One, HAST) If (HBDC) { - ShiftRight (And(Arg0, 2), 1, Local0) + ShiftRight (Arg0 & 2, 1, Local0) Store (Local0, \_SB.PCI0.LPCB.EC.BTEB) - ShiftRight (And(Arg0, 4), 2, Local0) + ShiftRight (Arg0 & 4, 2, Local0) Store (Local0, WBDC) } } @@ -226,9 +226,9 @@ Store (One, HAST) If (HWAN) { - ShiftRight (And(Arg0, 2), 1, Local0) + ShiftRight (Arg0 & 2, 1, Local0) Store (Local0, \_SB.PCI0.LPCB.EC.WWEB) - ShiftRight (And(Arg0, 4), 2, WWAN) + ShiftRight (Arg0 & 4, 2, WWAN) } } @@ -258,7 +258,7 @@ { If (HKBL) { /* FIXME: Support 2bit brightness control */ - Store (And(Arg0, 1), \_SB.PCI0.LPCB.EC.WWEB) + Store (Arg0 & 1, \_SB.PCI0.LPCB.EC.WWEB) } } @@ -288,7 +288,7 @@ Method (SUWB, 1) { If (HUWB) { - ShiftRight (And(Arg0, 2), 1, Local0) + ShiftRight (Arg0 & 2, 1, Local0) Store (Local0, \_SB.PCI0.LPCB.EC.UWBE) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/60723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id600bcb3fad35455adffe11a8105ad2590e83feb Gerrit-Change-Number: 60723 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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