coreboot-gerrit January 2022

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Change in coreboot[master]: mb/starlabs/labtop: Replace leading whitespace with tab
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60733 ) Change subject: mb/starlabs/labtop: Replace leading whitespace with tab ...................................................................... mb/starlabs/labtop: Replace leading whitespace with tab Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4d7324148ba182d0317b1f64e39f04a8a55fe79b --- M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/60733/1 diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 6c1217d..85e996c 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -21,7 +21,7 @@ register "CnviBtAudioOffload" = "1" register "enable_c6dram" = "1" register "SaGv" = "SaGv_Enabled" - register "TcssD3ColdDisable" = "1" + register "TcssD3ColdDisable" = "1" # FSP Silicon # Serial I/O -- To view, visit https://review.coreboot.org/c/coreboot/+/60733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d7324148ba182d0317b1f64e39f04a8a55fe79b Gerrit-Change-Number: 60733 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#9). Change subject: soc/intel/common/cse: Implement HECI notify ...................................................................... soc/intel/common/cse: Implement HECI notify This patch implements required heci operation to perform prior to booting to OS after platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. Additionally, creates helper function to set D0I3 for all HECI devices. SoC code to implement the function `soc_heci_set_d0i3` while putting the entire HECI device lists into D0i3. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 85 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60732 ) Change subject: soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43 --- M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/smihandler.c 2 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/60732/1 diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 9adc5b0..05ec99c 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,10 +134,6 @@ uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 2ca2816..a07aed7 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_icelake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43 Gerrit-Change-Number: 60732 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition
by Sridhar Siricilla (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Michael Niewöhner. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59358 ) Change subject: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/59358/comment/45711efe_b15cb981 PS7, Line 9: The patch move > `This patch moves the` Ack https://review.coreboot.org/c/coreboot/+/59358/comment/80cd66e0_4ce56208 PS7, Line 10: method get > `method will get called from cpu/intel/common in a later patch` Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc Gerrit-Change-Number: 59358 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 03 Jan 2022 19:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60731 ) Change subject: soc/intel/adl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/adl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/smihandler.c 8 files changed, 1 insertion(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60731/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 4662b95..2ba2889 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,9 +17,6 @@ # DPTF enable register "dptf_enable" = "1" - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b330e98..16517c5 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,9 +19,6 @@ register "tcc_offset" = "10" # TCC of 90 - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 2c45e85..a272c1b 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration # Enable CNVi BT diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index b73ded1..7707bf5 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -18,9 +18,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 communication - register "HeciEnabled" = "1" - # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index cec0422..f013596 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration # Enable CNVi BT diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5757392..63d3da4 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}" - # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi Bluetooth register "CnviBtCore" = "true" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 771fc5a..5b52214 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -310,10 +310,6 @@ } IgdDvmt50PreAlloc; uint8_t SkipExtGfxScan; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 5b53038..f842ddd 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_alderlake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 Gerrit-Change-Number: 60731 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake, soc/common: Add method to determine the cpu type
by Sridhar Siricilla (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Arthur Heymans, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59360 to look at the new patch set (#10). Change subject: soc/intel/alderlake, soc/common: Add method to determine the cpu type ...................................................................... soc/intel/alderlake, soc/common: Add method to determine the cpu type set_cpu_type(): It determines the CPU type (big or small) that is executing the function, and marks the global_cpu_type's array slot which is corresponds to the executing CPU's index if the CPU type is big core. get_cpu_index(): It determines the index from LAPIC Ids. This is required to expose CPPC3 package in ascending order of CPUs' LAPIC ids. So, the function returns CPU's position from the ascending order list of LAPIC ids. get_soc_cpu_type(): It returns the type of CPU that executing the function. Also, it calls the set_cpu_type() from soc/alderlake/cpu.c file. TEST=Tested CPU index calculation, core type determination on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b --- M src/soc/intel/alderlake/cpu.c M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 5 files changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/59360/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/59360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4ceb24d9bb1e808750bf618c29b2b9ea6d4191b Gerrit-Change-Number: 59360 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition
by Sridhar Siricilla (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Arthur Heymans, Michael Niewöhner. Hello Lance Zhao, build bot (Jenkins), Tim Wawrzynczak, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59358 to look at the new patch set (#9). Change subject: src/include/acpi: Move CPPC_PACKAGE_NAME macro definition ...................................................................... src/include/acpi: Move CPPC_PACKAGE_NAME macro definition The patch moves the CPPC_PACKAGE_NAME macro definition from file acpi/acpigen.c to include/acpi/acpigen.h file since the CPPC_PACKAGE_NAME method will get called from cpu/intel/common in a later patch. TEST=Built the code for Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/59358/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/59358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic547445cdbe2b1a3efe44390bd127f577386e7fc Gerrit-Change-Number: 59358 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
by Sridhar Siricilla (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Arthur Heymans, Nico Huber, Tim Wawrzynczak, Paul Menzel, Ravindra, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 ) Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/59359/comment/f06bf07d_cf0674e9 PS3, Line 102: acpi_get_cpu_hybrid_info(&cpu_hybrid_info); : acpigen_write_method(XPPC_PACKAGE_NAME, 1); : : if (cpu_is_nominal_freq_supported()) { : : /* : * If Nominal Frequency is supported, update Nominal Frequency and set core's : * Nominal Performance to a scaling factor which depends on core type(big or : * small). : */ : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 22, : cpu_hybrid_info.nominal_freq); : : /* LOCAL2_OP = (CORE >> core_id) & 1 */ : acpigen_emit_byte(SHIFT_RIGHT_OP); : acpigen_write_integer(cpu_hybrid_info.type_mask); : acpigen_emit_byte(ARG0_OP); : acpigen_emit_byte(LOCAL1_OP); : acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP); : : /* : * If core id is big Core, then set big core's scaling factor : * to core's nominal frequency otherwise set small core's scaling factor. : */ : acpigen_write_if_lequal_op_int(LOCAL2_OP, 1); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.big_core_nom_perf); : acpigen_write_else(); : acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3, : cpu_hybrid_info.small_core_nom_perf); : acpigen_pop_len(); : } : : acpigen_emit_byte(RETURN_OP); : acpigen_emit_namestring(CPPC_PACKAGE_NAME); : acpigen_pop_len(); > Is it worth it to implement it fully in SSDT? It looks like you could implement it in DSDT and just […] Implementing CPPCv3 package generation in the SSDT gives more flexibility. For example, CPPCv3 generation is not required for all the SoC variants (ADL-N/ADL-P) within the same CPU family(ADL). So, the CPPCv3 generation can be controlled through SoC function cpu_is_nominal_freq_supported() based on the SoC variant. -- To view, visit https://review.coreboot.org/c/coreboot/+/59359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd5ea9e70bebd1e66d3cea2bcf8a6678e5cc95ca Gerrit-Change-Number: 59359 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 19:15:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tgl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60730 ) Change subject: soc/intel/tgl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/tgl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb M src/mainboard/system76/darp7/devicetree.cb M src/mainboard/system76/galp5/devicetree.cb M src/mainboard/system76/gaze16/devicetree.cb M src/mainboard/system76/lemp10/devicetree.cb M src/mainboard/system76/oryp8/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/smihandler.c 11 files changed, 6 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/60730/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a93a38a..0e48756 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -87,9 +87,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # Enable heci communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 201983c..e0c0812 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d76c0f5..edd731a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_C" register "pmc_gpe0_dw2" = "GPP_D" - # Enable heci1 communication - register "HeciEnabled" = "1" - # FSP configuration register "SaGv" = "SaGv_Disabled" diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb index 35c2010..6c1217d 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb @@ -20,7 +20,6 @@ register "CnviBtCore" = "true" register "CnviBtAudioOffload" = "1" register "enable_c6dram" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "TcssD3ColdDisable" = "1" diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 75b0836..0d62c22 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -242,9 +242,7 @@ # TODO: USB-PD? register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb index 880da1e..604672a 100644 --- a/src/mainboard/system76/galp5/devicetree.cb +++ b/src/mainboard/system76/galp5/devicetree.cb @@ -253,9 +253,7 @@ # TODO: Pantone ROM? register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/gaze16/devicetree.cb b/src/mainboard/system76/gaze16/devicetree.cb index 8b43202..a92f044 100644 --- a/src/mainboard/system76/gaze16/devicetree.cb +++ b/src/mainboard/system76/gaze16/devicetree.cb @@ -123,9 +123,7 @@ device i2c 15 on end end end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index 96ee0a1..b1e28fc 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -223,9 +223,7 @@ # TODO: USB-PD? register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/mainboard/system76/oryp8/devicetree.cb b/src/mainboard/system76/oryp8/devicetree.cb index e6372fd..14a514f 100644 --- a/src/mainboard/system76/oryp8/devicetree.cb +++ b/src/mainboard/system76/oryp8/devicetree.cb @@ -158,9 +158,7 @@ device i2c 2c on end end end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref uart2 on # Debug console register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index fb0d827..a911ac5 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -274,10 +274,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 6280fb2..fba0fab 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_tigerlake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/60730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Gerrit-Change-Number: 60730 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool.h: util/ifdtool.c: Add additional regions for platforms...
by Name of user not set (Code Review) 03 Jan '22

03 Jan '22

Name of user not set #1004065 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60729 ) Change subject: util/ifdtool.h: util/ifdtool.c: Add additional regions for platforms that support them. Add Denverton platform support. ...................................................................... util/ifdtool.h: util/ifdtool.c: Add additional regions for platforms that support them. Add Denverton platform support. Change-Id: Ic8a4f26d833b1e628b7a72518d0a27252ec62f7c Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 50 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/60729/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ca5d3b8..e577b85 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -40,10 +40,17 @@ { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, - { "Reserved", "res1", "flashregion_5_reserved.bin", NULL }, - { "Reserved", "res2", "flashregion_6_reserved.bin", NULL }, + { "Device Expansion 1", "devexp", "flashregion_5_device_expansion.bin", "SI_DEV_EXP1" }, + { "Secondary BIOS", "bios2", "flashregion_6_bios2.bin", "SI_BIOS2" }, { "Reserved", "res3", "flashregion_7_reserved.bin", NULL }, { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, + { "Reserved", "res4", "flashregion_9_reserved.bin", NULL }, + { "IE", "ie", "flashregion_10_ie.bin", "SI_IE" }, + { "10GbA", "10gba", "flashregion_11_10gbeA.bin", "SI_10GBA" }, + { "10GbB", "10gbb", "flashregion_12_10gbeB.bin", "SI_10GBB" }, + { "Reserved", "res6", "flashregion_13_reserved.bin", NULL }, + { "Reserved", "res7", "flashregion_14_reserved.bin", NULL }, + { "PTT", "ptt", "flashregion_15_ptt.bin", "SI_PTT"} }; /* port from flashrom */ @@ -78,6 +85,7 @@ "400 series Ice Point", "500 series Tiger Point/ 600 series Alder Point", "C620 series Lewisburg", + "Denverton", NULL }; @@ -229,6 +237,8 @@ return CHIPSET_400_SERIES_ICE_POINT; case PLATFORM_LBG: return CHIPSET_C620_SERIES_LEWISBURG; + case PLATFORM_DNV: + return CHIPSET_DENVERTON; default: return CHIPSET_PCH_UNKNOWN; } @@ -253,6 +263,7 @@ PLATFORM_EHL, PLATFORM_ADL, PLATFORM_SKLKBL, + PLATFORM_DNV, }; unsigned int i; @@ -718,6 +729,12 @@ (flmstr & (1 << (wr_shift + 1))) ? "enabled" : "disabled"); printf(" Flash Descriptor Write Access: %s\n", (flmstr & (1 << wr_shift)) ? "enabled" : "disabled"); + if (platform == PLATFORM_DNV) { + printf(" 10GB A Region Write Access: %s\n", + (flmstr & (1 << (wr_shift + 11))) ? "enabled" : "disabled"); + printf(" 10GB B Region Write Access: %s\n", + (flmstr & (1 << (wr_shift + 12))) ? "enabled" : "disabled"); + } if (ifd_version >= IFD_VERSION_2) printf(" EC Region Read Access: %s\n", @@ -733,6 +750,12 @@ (flmstr & (1 << (rd_shift + 1))) ? "enabled" : "disabled"); printf(" Flash Descriptor Read Access: %s\n", (flmstr & (1 << rd_shift)) ? "enabled" : "disabled"); + if (platform == PLATFORM_DNV) { + printf(" 10GB A Region Read Access: %s\n", + (flmstr & (1 << (rd_shift + 11))) ? "enabled" : "disabled"); + printf(" 10GB B Region Read Access: %s\n", + (flmstr & (1 << (rd_shift + 12))) ? "enabled" : "disabled"); + } /* Requestor ID doesn't exist for ifd 2 */ if (ifd_version < IFD_VERSION_2) @@ -1631,6 +1654,7 @@ " adl - Alder Lake\n" " aplk - Apollo Lake\n" " cnl - Cannon Lake\n" + " dnv - Denverton\n" " lbg - Lewisburg PCH\n" " ehl - Elkhart Lake\n" " glk - Gemini Lake\n" @@ -1642,7 +1666,7 @@ " -V | --newvalue The new value to write into PCH strap specified by -S\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" - "<region> is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3\n" + "<region> is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3, EC, 10GB[A/B], PDR\n" "\n"); } @@ -1735,12 +1759,24 @@ region_type = 4; else if (!strcasecmp("res1", region_type_string)) region_type = 5; + else if (!strcasecmp("Device", region_type_string)) + region_type = 5; else if (!strcasecmp("res2", region_type_string)) region_type = 6; + else if (!strcasecmp("Secondary", region_type_string)) + region_type = 6; else if (!strcasecmp("res3", region_type_string)) region_type = 7; else if (!strcasecmp("EC", region_type_string)) region_type = 8; + else if (!strcasecmp("IE", region_type_string)) + region_type = 10; + else if (!strcasecmp("10GbA", region_type_string)) + region_type = 11; + else if (!strcasecmp("10GbB", region_type_string)) + region_type = 12; + else if (!strcasecmp("PTT", region_type_string)) + region_type = 15; if (region_type == -1) { fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); @@ -1875,6 +1911,8 @@ platform = PLATFORM_APL; } else if (!strcmp(optarg, "cnl")) { platform = PLATFORM_CNL; + } else if (!strcmp(optarg, "dnv")) { + platform = PLATFORM_DNV; } else if (!strcmp(optarg, "lbg")) { platform = PLATFORM_LBG; } else if (!strcmp(optarg, "ehl")) { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 4f63e20..2dd6ed6 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -45,6 +45,7 @@ CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) * variants onwards */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_DENVERTON, }; enum platform { @@ -58,6 +59,7 @@ PLATFORM_SKLKBL, PLATFORM_TGL, PLATFORM_ADL, + PLATFORM_DNV, }; #define LAYOUT_LINELEN 80 @@ -117,7 +119,7 @@ } __attribute__((packed)) fdbar_t; // regions -#define MAX_REGIONS 9 +#define MAX_REGIONS 16 #define MAX_REGIONS_OLD 5 enum flash_regions { @@ -126,7 +128,13 @@ REGION_ME, REGION_GBE, REGION_PDR, + REGION_DEV_EXP1, + REGION_BIOS2, REGION_EC = 8, + REGION_IE = 10, + REGION_10GBA, + REGION_10GBB, + REGION_PTT = 15, }; typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/60729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8a4f26d833b1e628b7a72518d0a27252ec62f7c Gerrit-Change-Number: 60729 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1004065 Gerrit-MessageType: newchange

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