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Change subject: mb/google/volteer/lindar: Probe for RT1011_ALC5682I_I2S
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60327/comment/392758d0_58ce6676
PS1, Line 10: being
`to be disabled`
Patchset:
PS1:
> Tim, is there a corresponding commit in the Chromium repositories?
No, I actually think this is an oversight... Lindar is the only volteer variant to use this audio option, so it may have been missed.
AP firmware for ChromeOS devices has its own stable branch that no longer tracks master past a certain point (volteer devices are long past this point), so
production firmware will only come from that branch now.
On the branch, the UPDs are set up so that the DSP will be enabled (PchHdaDspEnable), but the HD audio device will not; because of this, I suspect
this is mostly a resource (read: PCI resources) issue which will be corrected by the kernel, as the UPDs seem to require HDA to be enabled b/c of the DSP.
Felix, could you post logs before and after this? also lspci before and after?
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Change subject: [WIP]src: Remove unused <symbols.h>
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Change subject: mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane Parameter
......................................................................
Patch Set 3: Code-Review+2
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Change subject: arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I rebased the patches so that all related follow each other and in preparation to build-test them.
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Change subject: util: Allow installing to a build root
......................................................................
Patch Set 2:
(1 comment)
File util/ectool/Makefile:
https://review.coreboot.org/c/coreboot/+/60540/comment/6fe1db90_db08edf6
PS1, Line 8: PREFIX ?= /usr/local
> Actually that is a GNU extension, and not really needed [1], as it can be overridden by: […]
Dropped the change.
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Hello Felix Singer, build bot (Jenkins), Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60540
to look at the new patch set (#2).
Change subject: util: Allow installing to a build root
......................................................................
util: Allow installing to a build root
Modify util Makefiles to allow installing to a build root specified by
DESTDIR. Allows using the `install` target for packaging.
Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M util/ectool/Makefile
M util/pmh7tool/Makefile
M util/spkmodem_recv/Makefile
3 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/60540/2
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Change subject: ec/starlabs/merlin: Apply EC settings when suspending
......................................................................
Patch Set 13:
(1 comment)
File src/ec/starlabs/merlin/acpi/suspend.asl:
https://review.coreboot.org/c/coreboot/+/60165/comment/37afe5e5_19a096a0
PS12, Line 10: \_SB.PCI0.LPCB.TPLC = \_SB.PCI0.LPCB.EC.TPLE
> Can you please elaborate in the commit message, why the assignment was switched? So before, the valu […]
Done, and yes they were.
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Hello build bot (Jenkins), Andy Pont,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60165
to look at the new patch set (#13).
Change subject: ec/starlabs/merlin: Apply EC settings when suspending
......................................................................
ec/starlabs/merlin: Apply EC settings when suspending
Currently, the settings from CMOS were written to the
EC, which was pointless.
Now, when suspending, the EC values are stored in CMOS
when suspending and subsequently restored when waking.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf
---
M src/ec/starlabs/merlin/acpi/suspend.asl
1 file changed, 11 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/60165/13
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Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
......................................................................
Patch Set 13: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60341/comment/25ed075b_ddaa800f
PS13, Line 9: Taeko will use two PCIE port signals with one slot, one CLK and one
mention this is for the next build phase (so we understand why it won't apply to taeko4es)
https://review.coreboot.org/c/coreboot/+/60341/comment/b2ef7752_d31e9137
PS13, Line 14: Test on takeo trace in FSP log can find the correct root ports have
: been set depending on CBI.
```
Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME.
```
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