coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

1 participants
6716 discussions

Change in coreboot[master]: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Felix Singer, Erik van den Bogaert, Michał Żygowski, Frans Hendriks, Michael Niewöhner, Patrick Rudolph, Piotr Król. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60722 ) Change subject: soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config ...................................................................... soc/intel/skl: Replace dt `HeciEnabled` by `CSE disable` config Lists of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards selects DISABLE_CSE_AT_PRE_BOOT config to make CSE function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make CSE enable during boot don't select `cse disable` config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/Kconfig M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/Kconfig M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/finalize.c 32 files changed, 15 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60722/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index ac1b45d..ab8787c 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -47,7 +47,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 3a55f9e..096089f 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DISABLE_CSE_AT_PRE_BOOT select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index aed9184..a45127c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -101,9 +101,6 @@ device pci 15.3 off end # I2C #3 device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 - - # FIXME: does not match devicetree! - register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index db4d1ac..d22f574 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -60,9 +60,7 @@ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left end device ref thermal on end - device ref heci1 on - register "HeciEnabled" = "1" - end + device ref heci1 on end device ref sata on register "SataSalpSupport" = "0" # Ports diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 50738f4..f5d860d 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -4,6 +4,7 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select DISABLE_ACPI_HIBERNATE + select DISABLE_CSE_AT_PRE_BOOT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 023ace9..05bcc12 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ @@ -224,6 +223,7 @@ device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 007cbc7..6720681 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_MAX98927 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c731005..1e9ffd9 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -43,7 +43,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index afb2831..3f7147e 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_I2C_GENERIC select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index ceca5f1..5ecc77b 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -74,7 +74,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 04a48f7..f996bcb 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index a200cfb..9a3e619 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -42,7 +42,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 4a19f86..64ce0a6 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 39b7d9f..d26f6bd 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -50,7 +50,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4d145e1..db4aeeb 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -38,7 +38,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 6d7541e..7609e00 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -37,7 +37,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 068a031..b8a1812 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -38,7 +38,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index e4e0158..03336f2 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -43,7 +43,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index ff06d6a..c6c2d3d 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -50,7 +50,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 9be000f..5c34792 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -38,7 +38,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 2abf832..6e66ef2 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,6 +1,7 @@ config BOARD_INTEL_KBLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b7..bae619811 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ register "dptf_enable" = "1" # FSP Configuration - register "HeciEnabled" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 85f9e54..2ef19d1 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ba4835e..deb9f38 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -25,7 +25,6 @@ register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index d047f76..39c2e33 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -46,7 +46,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index a264c6b..feb8b9f 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,7 +34,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 4c6f6a8..b989188 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -1,6 +1,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n select BOARD_ROMSIZE_KB_16384 + select DISABLE_CSE_AT_PRE_BOOT select DRIVERS_GENERIC_CBFS_SERIAL select GFX_GMA_IGNORE_PRESENCE_STRAPS select HAVE_ACPI_RESUME diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index dfa894b..ef898b2 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -52,7 +52,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 3d311a3..3b2343b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -31,7 +31,6 @@ register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a048699..2e4e88c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -410,11 +410,11 @@ tconfig->PowerLimit4 = 0; /* * To disable HECI, the Psf needs to be left unlocked - * by FSP till end of post sequence. Based on the devicetree + * by FSP till end of post sequence. Based on the config * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; + tconfig->PchSbAccessUnlock = CONFIG(DISABLE_CSE_AT_PRE_BOOT); const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; tconfig->PchLockDownBiosInterface = lockdown_by_fsp; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 08d5d0f..12a6ae97 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,11 +395,6 @@ * 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - /* - * HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS - */ - u8 HeciEnabled; /* * Enable VR specific mailbox command diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 83bd3ae..28fbfa9 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -62,8 +62,8 @@ */ pch_thermal_configuration(); - /* we should disable Heci1 based on the devicetree policy */ - if (config->HeciEnabled == 0) + /* we should disable Heci1 based on the config */ + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT)) pch_disable_heci(); /* Hide p2sb device as the OS must not change BAR0. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/60722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Gerrit-Change-Number: 60722 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common/cse: Add config to disable CSE at pre-boot
by Subrata Banik (Code Review) 03 Jan '22

03 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60721 ) Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot ...................................................................... soc/intel/common/cse: Add config to disable CSE at pre-boot This patch adds a config to let mainboard users choose the correct state of CSE/Heci1 device prior to handing off to payload. `DISABLE_CSE_AT_PRE_BOOT` config to make CSE function disable at pre-boot. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/60721/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index ec901ca..ded46ee 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -5,8 +5,18 @@ Driver for communication with Converged Security Engine (CSE) over Host Embedded Controller Interface (HECI) +config DISABLE_CSE_AT_PRE_BOOT + bool "Disable CSE at the end of boot" + depends on SOC_INTEL_COMMON_BLOCK_CSE + default n + help + This config decides the state of CSE/Heci1 device at the end of boot. + Mainboard users to select this config to make CSE `function disable` prior + to handing off to payload. + config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM bool + depends on DISABLE_CSE_AT_PRE_BOOT default y if HECI_DISABLE_USING_SMM select SOC_INTEL_COMMON_BLOCK_P2SB help -- To view, visit https://review.coreboot.org/c/coreboot/+/60721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a Gerrit-Change-Number: 60721 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/acpi: Replace Store() with ASL 2.0 syntax
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60720 ) Change subject: arch/x86/acpi: Replace Store() with ASL 2.0 syntax ...................................................................... arch/x86/acpi: Replace Store() with ASL 2.0 syntax Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/arch/x86/acpi/debug.asl M src/arch/x86/acpi/globutil.asl 2 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/60720/1 diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index e6dfe6a..b6433bf 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -36,12 +36,12 @@ */ Method(DINI) { - store(0x83, DLCR) - store(0x01, CDAT) /* 115200 baud (low) */ - store(0x00, CDLM) /* 115200 baud (high) */ - store(0x03, DLCR) /* word=8 stop=1 parity=none */ - store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */ - store(0x00, CDLM) /* turn off interrupts */ + DLCR = 0x83 + CDAT = 1 /* 115200 baud (low) */ + CDLM = 0 /* 115200 baud (high) */ + DLCR = 3 /* word=8 stop=1 parity=none */ + CMCR = 3 /* DTR=1 RTS=1 Out2=Off Loop=Off */ + CDLM = 0 /* turn off interrupts */ } /* @@ -63,7 +63,7 @@ Method(OUTX, 1) { THRE() - store(Arg0, CDAT) + CDAT = Arg0 } /* @@ -145,10 +145,10 @@ } } else { Name(BDBG, Buffer(80) {}) - store(Arg0, BDBG) - store(0, Local1) + BDBG = Arg0 + Local1 = 0 while (One) { - store(GETC(BDBG, Local1), Local0) + Local0 = GETC(BDBG, Local1) if (Local0 == 0) { return (0) } diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index e9bbcfe..8192cf3 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -18,7 +18,7 @@ Method(SLEN, 1) { - Store(Arg0, Local0) + Local0 = Arg0 Return(Sizeof(Local0)) } @@ -26,23 +26,23 @@ { Local0 = SLEN(Arg0) + 1 Name(BUFF, Buffer(Local0) {}) - Store(Arg0, BUFF) + BUFF = Arg0 Return(BUFF) } /* Strong string compare. Checks both length and content */ Method(SCMP, 2) { - Store(S2BF(Arg0), Local0) - Store(S2BF(Arg1), Local1) - Store(Zero, Local4) - Store(SLEN(Arg0), Local5) - Store(SLEN(Arg1), Local6) - Store(MIN(Local5, Local6), Local7) + Local0 = S2BF(Arg0) + Local1 = S2BF(Arg1) + Local4 = 0 + Local5 = SLEN(Arg0) + Local6 = SLEN(Arg1) + Local7 = MIN(Local5, Local6) While(Local4 < Local7) { - Store(Derefof(Local0[Local4]), Local2) - Store(Derefof(Local1[Local4]), Local3) + Local2 = Derefof(Local0[Local4]) + Local3 = Derefof(Local1[Local4]) if (Local2 > Local3) { Return(One) } else { @@ -69,13 +69,13 @@ */ Method(WCMP, 2) { - Store(S2BF(Arg0), Local0) - Store(S2BF(Arg1), Local1) + Local0 = S2BF(Arg0) + Local1 = S2BF(Arg1) if (SLEN(Arg0) < SLEN(Arg1)) { Return(0) } - Store(Zero, Local2) - Store(SLEN(Arg1), Local3) + Local2 = 0 + Local3 = SLEN(Arg1) While(Local2 < Local3) { if (Derefof(Local0[Local2]) != Derefof(Local1[Local2])) { @@ -91,9 +91,9 @@ */ Method(I2BM, 1) { - Store(0, Local0) + Local0 = 0 if (ARG0 != 0) { - Store(1, Local1) + Local1 = 1 Local0 = Local1 << ARG0 } Return(Local0) -- To view, visit https://review.coreboot.org/c/coreboot/+/60720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a Gerrit-Change-Number: 60720 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/acpi: Replace And() with ASL 2.0 syntax
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60719 ) Change subject: arch/x86/acpi: Replace And() with ASL 2.0 syntax ...................................................................... arch/x86/acpi: Replace And() with ASL 2.0 syntax Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/arch/x86/acpi/debug.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/60719/1 diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index 7b0aec4..e6dfe6a 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -50,9 +50,9 @@ */ Method(THRE) { - and(CLSR, 0x20, local0) + local0 = CLSR & 0x20 while (local0 == 0) { - and(CLSR, 0x20, local0) + local0 = CLSR & 0x20 } } @@ -84,7 +84,7 @@ */ Method(DBGN, 1) { - and(Arg0, 0x0f, Local0) + Local0 = Arg0 & 0x0f if (Local0 < 10) { Local0 += 0x30 } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/60719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7 Gerrit-Change-Number: 60719 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntax
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60718 ) Change subject: arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntax ...................................................................... arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntax Change-Id: I493d686fb122fb47f0b4dcf34e3635518770f97f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/arch/x86/acpi/globutil.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60718/1 diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index 2ea4f96..e9bbcfe 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -94,7 +94,7 @@ Store(0, Local0) if (ARG0 != 0) { Store(1, Local1) - ShiftLeft(Local1, ARG0, Local0) + Local0 = Local1 << ARG0 } Return(Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/60718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I493d686fb122fb47f0b4dcf34e3635518770f97f Gerrit-Change-Number: 60718 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntax
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60717 ) Change subject: arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntax ...................................................................... arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntax Change-Id: Iaa99d9dc4cf12a7431be1610d339cf78116f8bea Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/arch/x86/acpi/debug.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/60717/1 diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index ed1c60d..7b0aec4 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -99,7 +99,7 @@ */ Method(DBGB, 1) { - ShiftRight(Arg0, 4, Local0) + Local0 = Arg0 >> 4 DBGN(Local0) DBGN(Arg0) } @@ -110,7 +110,7 @@ */ Method(DBGW, 1) { - ShiftRight(Arg0, 8, Local0) + Local0 = Arg0 >> 8 DBGB(Local0) DBGB(Arg0) } @@ -121,7 +121,7 @@ */ Method(DBGD, 1) { - ShiftRight(Arg0, 16, Local0) + Local0 = Arg0 >> 16 DBGW(Local0) DBGW(Arg0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/60717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa99d9dc4cf12a7431be1610d339cf78116f8bea Gerrit-Change-Number: 60717 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/boten: Add Wifi SAR for bookem
by Karthik Ramasubramanian (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Henry Sun, Stanley Wu, Paul Fagerburg. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60399 ) Change subject: mb/google/dedede/var/boten: Add Wifi SAR for bookem ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e5bac662fb44cf631ae1453068dec898b6e2607 Gerrit-Change-Number: 60399 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 17:59:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCR
by Karthik Ramasubramanian (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Zhi7 Li. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60337 ) Change subject: mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCR ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Please rebase this CL to resolve the jenkins build failure. The build failure is not related to this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/60337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic436db8fe3ef6fb8379ec629b128c05c691ea6fe Gerrit-Change-Number: 60337 Gerrit-PatchSet: 3 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Jan 2022 17:57:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/lindar: Probe for RT1011_ALC5682I_I2S
by Felix Singer (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel, Nick Vaccaro. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60327 ) Change subject: mb/google/volteer/lindar: Probe for RT1011_ALC5682I_I2S ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Tim, is there a corresponding commit in the Chromium repositories? I went through the ChromiumOS branches and this seems to be the only difference. I think these controllers were added in one patch, but this one was forgotten during the upstreaming process. > Felix, could you post logs before and after this? also lspci before and after? Will do. -- To view, visit https://review.coreboot.org/c/coreboot/+/60327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib848b65b4939dd43d78cb7fd7b8b271e95f324be Gerrit-Change-Number: 60327 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 17:45:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/bugzzy: Initialize display signals on user mode
by Karthik Ramasubramanian (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: shkim, Henry Sun, Evan Green, Tim Wawrzynczak, SH Kim, Paul Menzel, Simon Yang, Edward Doan. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60190 ) Change subject: mb/google/dedede/var/bugzzy: Initialize display signals on user mode ...................................................................... Patch Set 14: Code-Review+2 (1 comment) File src/mainboard/google/dedede/variants/bugzzy/ramstage.c: https://review.coreboot.org/c/coreboot/+/60190/comment/d17ee37f_09d9582a PS13, Line 61: > Verified-1 is coming from the extra newline here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/60190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db Gerrit-Change-Number: 60190 Gerrit-PatchSet: 14 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: shkim <sh_.kim(a)samsung.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Edward Doan <edoan(a)google.com> Gerrit-Comment-Date: Mon, 03 Jan 2022 17:36:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2022