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Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/59359/comment/65d82019_b249bbf5
PS3, Line 102: acpi_get_cpu_hybrid_info(&cpu_hybrid_info);
: acpigen_write_method(XPPC_PACKAGE_NAME, 1);
:
: if (cpu_is_nominal_freq_supported()) {
:
: /*
: * If Nominal Frequency is supported, update Nominal Frequency and set core's
: * Nominal Performance to a scaling factor which depends on core type(big or
: * small).
: */
: acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 22,
: cpu_hybrid_info.nominal_freq);
:
: /* LOCAL2_OP = (CORE >> core_id) & 1 */
: acpigen_emit_byte(SHIFT_RIGHT_OP);
: acpigen_write_integer(cpu_hybrid_info.type_mask);
: acpigen_emit_byte(ARG0_OP);
: acpigen_emit_byte(LOCAL1_OP);
: acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP);
:
: /*
: * If core id is big Core, then set big core's scaling factor
: * to core's nominal frequency otherwise set small core's scaling factor.
: */
: acpigen_write_if_lequal_op_int(LOCAL2_OP, 1);
: acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3,
: cpu_hybrid_info.big_core_nom_perf);
: acpigen_write_else();
: acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3,
: cpu_hybrid_info.small_core_nom_perf);
: acpigen_pop_len();
: }
:
: acpigen_emit_byte(RETURN_OP);
: acpigen_emit_namestring(CPPC_PACKAGE_NAME);
: acpigen_pop_len();
> Implementing CPPCv3 package generation in the SSDT gives more flexibility. For example, CPPCv3 generation is not required for all the SoC variants (ADL-N/ADL-P) within the same CPU family(ADL). So, the CPPCv3 generation can be controlled through SoC function cpu_is_nominal_freq_supported() based on the SoC variant.
I don't see the code doing that.
Also why would implementing it fully in SSDT be more flexible than a DSDT implemenation consuming SSDT namespace (using the external keyword)?
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Change subject: ec/starlabs/merlin: Apply EC settings when suspending
......................................................................
Patch Set 13: Code-Review+1
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Change subject: util: Allow installing to a build root
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCR
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60337/comment/6d4da029_0fb2778c
PS3, Line 10: for the memory parts. The memory parts being added are:
: Samsung K4U6E3S4AA-MGCR
for Samsung K4U6E3S4AA-MGCR.
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Change subject: mb/google/dedede/var/boten: Add Wifi SAR for bookem
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60399/comment/ee4480e9_01faeba7
PS1, Line 9: Add new sku id apply for bookem wifi sar table.
Where did you get the values from?
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Change subject: ifdtool: dump all PCH Straps
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
Can this be submitted or rebased?
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Change subject: util/ifdtool.h: util/ifdtool.c: Add additional regions for platforms that support them. Add Denverton platform support.
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60729/comment/af6231fc_72ceec59
PS1, Line 7: util/ifdtool.h:
: util/ifdtool.c: Add additional regions for platforms that support them. Add Denverton platform support.
Please write the commit message in the common format (`git log` or *How to Write a Git Commit Message* [1]).
[1]: https://review.coreboot.org/q/status:openhttps://review.coreboot.org/c/coreboot/+/60729/comment/4f005fa4_b5a91e73
PS1, Line 8: Add Denverton platform support.
Please split it into two commits.
File util/ifdtool/ifdtool.h:
https://review.coreboot.org/c/coreboot/+/60729/comment/c7777a47_207fdb42
PS1, Line 62: PLATFORM_DNV,
Please sort it.
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Change subject: soc/intel/common/cse: Implement HECI notify
......................................................................
Patch Set 10:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60405/comment/4bd814f5_0a45ad0a
PS8, Line 9: required heci operation
> `the required HECI operations`
Ack
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/1ac0ad6f_22c3fa71
PS7, Line 279: HeciEnabled
> > Yes I have been on vacation, good guess 😄 […]
Kindly review below changes that I have attempted address our discussion above.
https://review.coreboot.org/q/topic:retire_hecienabled
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60405
to look at the new patch set (#10).
Change subject: soc/intel/common/cse: Implement HECI notify
......................................................................
soc/intel/common/cse: Implement HECI notify
This patch implements the required HECI operations to perform
prior to booting to OS after platform decides to skip FSP
notify APIs i.e. Ready to Boot and End Of Firmware.
Additionally, creates helper function to set D0I3 for all
HECI devices. SoC code to implement the function
`soc_heci_set_d0i3` while putting the entire HECI device
lists into D0i3.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with
this code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_HECI_NOTIFY:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 85 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/10
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