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Hello zanxi chen, Paul Menzel, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCR
......................................................................
mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AA-MGCR
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AA-MGCR.
BUG=b:211950312
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: Ic436db8fe3ef6fb8379ec629b128c05c691ea6fe
---
M src/mainboard/google/dedede/variants/storo/memory/Makefile.inc
M src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt
3 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/60337/4
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Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60617 )
Change subject: src/soc: Remove unused <stdlib.h>
......................................................................
Patch Set 2: Code-Review+2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60331 )
Change subject: mb/google/brya/var/vell: Add AMP driver setting
......................................................................
Patch Set 8:
(8 comments)
File src/drivers/i2c/cs35l53/cs35l53.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/6759bcbb_a24e1b08
PS8, Line 72: (config->boost_peak_milliamp % 50)){
space required before the open brace '{'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/df48ecf1_d4c505ba
PS8, Line 82: acpi_dp_add_integer(dsd, "cirrus,gpio1-polarity-invert", config->gpio1_polarity_invert ? 1 : 0);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/bebeb899_cd2762d8
PS8, Line 83: acpi_dp_add_integer(dsd, "cirrus,gpio1-output-enable", config->gpio1_output_enable ? 1 : 0);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/c705cbc2_2f87a429
PS8, Line 85: acpi_dp_add_integer(dsd, "cirrus,gpio2-polarity-invert", config->gpio2_polarity_invert ? 1 : 0);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/266bd685_961f9826
PS8, Line 86: acpi_dp_add_integer(dsd, "cirrus,gpio2-output-enable", config->gpio2_output_enable ? 1 : 0);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/672efaf9_51033144
PS8, Line 108: if (config->name){
suspect code indent for conditional statements (0, 0)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/f29fe609_32d099fe
PS8, Line 108: if (config->name){
space required before the open brace '{'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137124):
https://review.coreboot.org/c/coreboot/+/60331/comment/15b27cf0_44485b49
PS8, Line 108: if (config->name){
braces {} are not necessary for single statement blocks
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Robert Chen has uploaded a new patch set (#8) to the change originally created by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/60331 )
Change subject: mb/google/brya/var/vell: Add AMP driver setting
......................................................................
mb/google/brya/var/vell: Add AMP driver setting
update overridetree.cb
update Kconfig.name
update i2c/C35l53
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
---
A src/drivers/i2c/cs35l53/Kconfig
A src/drivers/i2c/cs35l53/Makefile.inc
A src/drivers/i2c/cs35l53/chip.h
A src/drivers/i2c/cs35l53/cs35l53.c
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/vell/gpio.c
M src/mainboard/google/brya/variants/vell/overridetree.cb
7 files changed, 336 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60331/8
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David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60388 )
Change subject: mb/google/brya/var/kano: Disable autonomous GPIO power management
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60388/comment/ab50fa04_87ddbef7
PS1, Line 7: disabled
> `Disable`
Done
https://review.coreboot.org/c/coreboot/+/60388/comment/e59c0529_113e47a3
PS1, Line 8:
: Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
: less to production that will need to disable autonomous GPIO power
: management and then can get H1 version by gsctool -a -f -M
> suggestion: […]
Done
Patchset:
PS3:
Thanks.
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/brya/var/kano: Disable autonomous GPIO power management
......................................................................
mb/google/brya/var/kano: Disable autonomous GPIO power management
When using cr50 FW 0.0.22/0.3.22 or earlier, its interrupt pulses
are too short to be detected when autonomous GPIO power management is enabled, therefore disable autonomous GPIO PM.
BUG=b:201266532
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: I9607af42a00c1b5f38c6e4e0effdeeaba18af5ff
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/60388/3
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60388
to look at the new patch set (#2).
Change subject: mb/google/brya/var/kano: disable autonomous GPIO power management
......................................................................
mb/google/brya/var/kano: disable autonomous GPIO power management
When using cr50 FW 0.0.22/0.3.22 or earlier, its interrupt pulses
are too short to be detected when autonomous GPIO power management is enabled, therefore disable autonomous GPIO PM.
BUG=b:201266532
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Change-Id: I9607af42a00c1b5f38c6e4e0effdeeaba18af5ff
---
M src/mainboard/google/brya/variants/kano/overridetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/60388/2
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Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60341 )
Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
......................................................................
Patch Set 14:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60341/comment/46526a26_d66b193b
PS13, Line 9: Taeko will use two PCIE port signals with one slot, one CLK and one
> mention this is for the next build phase (so we understand why it won't apply to taeko4es)
Updated in latest patchset.
https://review.coreboot.org/c/coreboot/+/60341/comment/11085588_fa693f93
PS13, Line 14: Test on takeo trace in FSP log can find the correct root ports have
: been set depending on CBI.
> ``` […]
Updated in latest patchset.
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