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Robert Chen has uploaded a new patch set (#9) to the change originally created by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/60331 )
Change subject: mb/google/brya/var/vell: Add AMP driver setting
......................................................................
mb/google/brya/var/vell: Add AMP driver setting
update overridetree.cb
update Kconfig.name
update i2c/C35l53
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
Change-Id: I96d49bd1a2ba061c4fd52b450b31d0885f49552c
---
A src/drivers/i2c/cs35l53/Kconfig
A src/drivers/i2c/cs35l53/Makefile.inc
A src/drivers/i2c/cs35l53/chip.h
A src/drivers/i2c/cs35l53/cs35l53.c
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/vell/gpio.c
M src/mainboard/google/brya/variants/vell/overridetree.cb
7 files changed, 290 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60331/9
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Hello Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60721
to look at the new patch set (#2).
Change subject: soc/intel/common/cse: Add config to disable CSE at pre-boot
......................................................................
soc/intel/common/cse: Add config to disable CSE at pre-boot
This patch adds a config to let mainboard users choose the correct
state of CSE/Heci1 device prior to handing off to payload.
`DISABLE_CSE_AT_PRE_BOOT` config to make CSE function disable at pre-boot.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a
---
M src/soc/intel/common/block/cse/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/60721/2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60737 )
Change subject: util/ifdtool: Add support for Denverton platforms.
......................................................................
Patch Set 1:
(3 comments)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/60737/comment/5d96d219_8b262f05
PS1, Line 716:
Maybe add
int has_10gbe_A = (platform == PLATFORM_DNV);
int has_10gbe_B = ...
and use those below
https://review.coreboot.org/c/coreboot/+/60737/comment/2fc9f76a_f94a798f
PS1, Line 732: if (platform == PLATFORM_DNV) {
Use the booleans from above.
if (has_10gbe_A)
https://review.coreboot.org/c/coreboot/+/60737/comment/679f7482_bb799c09
PS1, Line 733: printf(" 10GB A Region Write Access: %s\n",
10GbE is the common terminology?
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Change subject: mb/google/brya: Allow primus variant to choose eNEM CAR
......................................................................
Patch Set 1: Code-Review+2
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59359 )
Change subject: soc/intel/common: Implement ACPI CPPCv3 package to support hybrid core
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/common/block/acpi/cpu_hybrid.c:
https://review.coreboot.org/c/coreboot/+/59359/comment/6dbbf455_9826e00a
PS3, Line 102: acpi_get_cpu_hybrid_info(&cpu_hybrid_info);
: acpigen_write_method(XPPC_PACKAGE_NAME, 1);
:
: if (cpu_is_nominal_freq_supported()) {
:
: /*
: * If Nominal Frequency is supported, update Nominal Frequency and set core's
: * Nominal Performance to a scaling factor which depends on core type(big or
: * small).
: */
: acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 22,
: cpu_hybrid_info.nominal_freq);
:
: /* LOCAL2_OP = (CORE >> core_id) & 1 */
: acpigen_emit_byte(SHIFT_RIGHT_OP);
: acpigen_write_integer(cpu_hybrid_info.type_mask);
: acpigen_emit_byte(ARG0_OP);
: acpigen_emit_byte(LOCAL1_OP);
: acpigen_write_and(LOCAL1_OP, ONE_OP, LOCAL2_OP);
:
: /*
: * If core id is big Core, then set big core's scaling factor
: * to core's nominal frequency otherwise set small core's scaling factor.
: */
: acpigen_write_if_lequal_op_int(LOCAL2_OP, 1);
: acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3,
: cpu_hybrid_info.big_core_nom_perf);
: acpigen_write_else();
: acpigen_set_package_element_int(CPPC_PACKAGE_NAME, 3,
: cpu_hybrid_info.small_core_nom_perf);
: acpigen_pop_len();
: }
:
: acpigen_emit_byte(RETURN_OP);
: acpigen_emit_namestring(CPPC_PACKAGE_NAME);
: acpigen_pop_len();
> > Implementing CPPCv3 package generation in the SSDT gives more flexibility. […]
>I don't see the code doing that.
At the time of writing the code, ADL-N code was not exposed externally. I will add the code to enable it for ADL-N later.
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Change subject: util/ifdtool: Add additional regions for platforms that support them.
......................................................................
Patch Set 1:
(2 comments)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/60736/comment/6c6983b6_56d346b1
PS1, Line 88: "Denverton",
Move to next patch in the series.
https://review.coreboot.org/c/coreboot/+/60736/comment/e5fb443e_ab1a648e
PS1, Line 1653: "<region> is one of Descriptor, BIOS, ME, GbE, Platform, res1, res2, res3, EC, 10GB[A/B], PDR\n"
Shouldn't this match the strcasecmp() calls below?
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Change subject: drivers/intel/fsp2_0: Make FSP Notify Phase APIs optional
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> huh? I always thought the notify phases are required?
Yes, all FSP APIs are required unless we figured out an alternative approach. For an example: FSP-T was mandatory at one point then with coreboot started on its own implementing CAR native code for IA, we have made FSP-T optional.
> Does that mean, that they are not?
CB:60405 is the one attempted to make FSP-Notify Phase APIs (for now Ready to Boot and End of Firmware) optional. I will pick post-PCI enumeration sooner.
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60739 )
Change subject: mb/google/brya: Allow primus variant to choose eNEM CAR
......................................................................
mb/google/brya: Allow primus variant to choose eNEM CAR
More Brya variants like Primus have migrated to use Alder Lake
QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR
by default for primus variants.
BUG=b:168820083
TEST=Able to build and boot primus variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I65d12de08adf85140976e1a7659ad7b684aa75c8
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/60739/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b000baf..b359965 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -176,7 +176,7 @@
choice
prompt "Cache as RAM (CAR) setup configuration to use"
- default USE_ADL_ENEM if BOARD_GOOGLE_KANO || BOARD_GOOGLE_FELWINTER || BOARD_GOOGLE_REDRIX || BOARD_GOOGLE_GIMBLE || BOARD_GOOGLE_BRASK
+ default USE_ADL_ENEM if BOARD_GOOGLE_KANO || BOARD_GOOGLE_FELWINTER || BOARD_GOOGLE_REDRIX || BOARD_GOOGLE_GIMBLE || BOARD_GOOGLE_BRASK || BOARD_GOOGLE_PRIMUS
default USE_ADL_NEM
config USE_ADL_ENEM
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shkim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/59534 )
Change subject: mb/google/dedede/var/bugzzy: Pick the config VBOOT_ALWAYS_ENABLE_DISPLAY
......................................................................
Abandoned
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