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Hello Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57320
to look at the new patch set (#2).
Change subject: [WIP] soc/amd/picasso: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
[WIP] soc/amd/picasso: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section.
TODO: check if the EFS FMAP partition begins at the expected location
TEST=Mandolin which only uses one CBFS still boots. The case with RO/A/B
CBFS isn't tested.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I88824e4d0c1ead203f46f8cd64e1d1b4f1aa6cf7
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/57320/2
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Gerrit-Change-Id: I88824e4d0c1ead203f46f8cd64e1d1b4f1aa6cf7
Gerrit-Change-Number: 57320
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57321 )
Change subject: [TEST] mb/amd/mandolin: use AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
[TEST] mb/amd/mandolin: use AMD_SOC_SEPARATE_EFS_SECTION
Move the EFS to the lowest possible position inside the flash by adding
an EFS FMAP section right after the EC firmware FMAP section and
selecting AMD_SOC_SEPARATE_EFS_SECTION.
TEST=Mandolin still boots.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I372bcc60943a42b511cea1fdd451a15ad420a679
---
M src/mainboard/amd/mandolin/Kconfig
M src/mainboard/amd/mandolin/variants/mandolin/board.fmd
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/57321/1
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
index 50b3e5d..96f14ab 100644
--- a/src/mainboard/amd/mandolin/Kconfig
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -12,6 +12,7 @@
select HAVE_ACPI_RESUME
select DRIVERS_UART_ACPI
select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
+ select AMD_SOC_SEPARATE_EFS_SECTION if BOARD_AMD_MANDOLIN
config FMDFILE
default "src/mainboard/amd/mandolin/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
@@ -69,7 +70,6 @@
config AMD_FWM_POSITION_INDEX
int
- default 3 if BOARD_AMD_MANDOLIN
default 4 if BOARD_AMD_CEREME
help
TODO: might need to be adapted for better placement of files in cbfs
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd
index 33b281d..1296b85 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd
+++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd
@@ -1,6 +1,7 @@
FLASH@0xFF800000 8M {
BIOS {
EC 128K
+ EFS 3M
RW_MRC_CACHE 64K
FMAP 4K
COREBOOT(CBFS)
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Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57320 )
Change subject: [WIP] soc/amd/picasso: introduce AMD_SOC_SEPARATE_EFS_SECTION
......................................................................
[WIP] soc/amd/picasso: introduce AMD_SOC_SEPARATE_EFS_SECTION
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section.
TODO: check if the EFS FMAP partition begins at the expected location
TEST=Mandolin which only uses one CBFS still boots. The case with RO/A/B
CBFS isn't tested.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I88824e4d0c1ead203f46f8cd64e1d1b4f1aa6cf7
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/57320/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index addff5e..e079cd6 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -457,6 +457,14 @@
endmenu
+config AMD_SOC_SEPARATE_EFS_SECTION
+ bool
+ help
+ Use separate EFS FMAP section instead of putting EFS into CBFS. The
+ FMAP section must begin exactly at the location the EFS needs to be
+ placed in the flash. This option can be used to place the EFS right
+ after the 128kByte EC firmware at the beginning of the flash.
+
config VBOOT
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index d873079..b2d3071 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -268,10 +268,19 @@
--anywhere \
--output $@
+ifeq ($(CONFIG_AMD_SOC_SEPARATE_EFS_SECTION),y)
+$(call add_intermediate, amdfw_fmap_section)
+#FWM_POSITION_BASE=$(shell printf "%\#x" $(PICASSO_FWM_POSITION))
+#EFS_SECTION_BASE=$(shell awk '$$2 == "FMAP_SECTION_EFS_START" {print $$3}' $(obj)/fmap_config.h)
+#TODO: error out if FWM_POSITION_BASE != EFS_SECTION_BASE; depends on $(obj)/fmap_config.h bing generated though
+amdfw_fmap_section: $(obj)/coreboot.pre $(obj)/amdfw.rom $(obj)/fmap_config.h
+ $(CBFSTOOL) $(obj)/coreboot.pre write -r EFS -f $(obj)/amdfw.rom --fill-upward
+else # CONFIG_AMD_SOC_SEPARATE_EFS_SECTION
cbfs-files-y += apu/amdfw
apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(PICASSO_FWM_POSITION)
apu/amdfw-type := raw
+endif # CONFIG_AMD_SOC_SEPARATE_EFS_SECTION
ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy)
cbfs-files-y += apu/amdfw_a
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57061 )
Change subject: wifi: Add support for wifi time average SAR config
......................................................................
Patch Set 9:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/57061/comment/1c19768a_29e1cd51
PS9, Line 315: MAX_DENYLIST_ENTRY
can this be `wtas->tas_list_size` or do all 16 entries have to be there? (if so, why have a list size field 😕)
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Change subject: wifi: Add support for per-platform antenna gain
......................................................................
Patch Set 8: Code-Review+1
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56750 )
Change subject: wifi: Add support for new revisions of SAR table entries
......................................................................
Patch Set 25: Code-Review+1
(3 comments)
File src/vendorcode/google/chromeos/sar.c:
https://review.coreboot.org/c/coreboot/+/56750/comment/220b3f9b_dd2636b1
PS25, Line 59: (1 + sar->dsar_set_count)
comment why the `1 + ` is required?
https://review.coreboot.org/c/coreboot/+/56750/comment/2ba395c1_d52165bb
PS25, Line 99: void *
a `uint8_t *` should be able to cast to anything, this can be:
`struct sar_header *`
https://review.coreboot.org/c/coreboot/+/56750/comment/afbe0e3e_26ead37e
PS25, Line 220: !strncmp(sar_str, SAR_STR_PREFIX, SAR_STR_PREFIX_SIZE) != 0
extra `!` at the beginning
`if (strncmp(sar_str, SAR_STR_PREFIX, SAR_STR_PREFIX_SIZE) != 0)`
?
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Change subject: qualcomm/sc7180: Clean up drivers with common clock
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Patch Set 8: Code-Review+2
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