Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57299
to look at the new patch set (#5).
Change subject: mb/google/volteer: Add type-c port info to coreboot table
......................................................................
mb/google/volteer: Add type-c port info to coreboot table
This change adds type-c port information for USB type-c ports to the
coreboot table. This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
localhost ~ # cbmem -c | grep type-c
Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0
Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0
Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/volteer/mainboard.c
1 file changed, 35 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57299/5
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Gerrit-Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d
Gerrit-Change-Number: 57299
Gerrit-PatchSet: 5
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57069
to look at the new patch set (#11).
Change subject: coreboot tables: Add type-c port info to coreboot table
......................................................................
coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table. This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.
BUG=b:149830546
TEST='emerge-trogdor coreboot' and verify it builds.
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully. Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
localhost ~ # cbmem -c | grep type-c
Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0
Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
---
M payloads/libpayload/include/coreboot_tables.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
M src/commonlib/include/commonlib/coreboot_tables.h
M src/drivers/intel/pmc_mux/conn/chip.h
M src/drivers/intel/pmc_mux/conn/conn.c
M src/include/boot/coreboot_tables.h
M src/lib/coreboot_table.c
8 files changed, 166 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/11
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Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57033 )
Change subject: soc/intel/denverton_ns: Add early SPI flash init
......................................................................
Abandoned
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57149 )
Change subject: soc/tigerlake: Don't send CSE EOP if CSME is disabled
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/57149/comment/8ff1b788_6203b994
PS10, Line 111: return CSE_EOP_RESULT_DISABLED;
> One last thing, please modify like so: […]
Done
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56601 )
Change subject: tests: Add lib/cbfs-verification-test test case
......................................................................
Patch Set 11:
(1 comment)
File tests/include/tests/lib/cbfs_util.h:
https://review.coreboot.org/c/coreboot/+/56601/comment/3c75e84d_35091055
PS8, Line 74: TEST_REGION(cbfs_cache, TEST_CBFS_CACHE_SIZE);
> Ok, so I moved all globals (except cbfs_boot_device) to the mock file. […]
Julius, all good here?
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57293 )
Change subject: soc/amd/cezanne: Increase the FSP_M_SIZE configuration
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Submitted it since the CL has been active for more than 24 hours and it is required to unblock CI.
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