coreboot-gerrit September 2021

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Change in coreboot[master]: soc/amd/cezanne: Increase the FSP_M_SIZE configuration
by Karthik Ramasubramanian (Code Review) 01 Sep '21

01 Sep '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57293 ) Change subject: soc/amd/cezanne: Increase the FSP_M_SIZE configuration ...................................................................... soc/amd/cezanne: Increase the FSP_M_SIZE configuration On mainboards with Cezanne SOC, serial enabled FSP_M binary size is greater than the size allocated in DRAM. Increase the allocated size for FSP_M binary in DRAM to handle both debug and release FSP_M binaries. Also adjust the verstage load address accordingly. BUG=None TEST=Build and boot to OS in guybrush with both debug and release FSP_M. Perform warm, cold reboot and suspend/resume cycling for 10 iterations. Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 81597d0..46e6017 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -166,7 +166,7 @@ config FSP_M_SIZE hex - default 0x80000 + default 0xC0000 help Sets the size of DRAM allocation for FSP-M in linker script. @@ -179,7 +179,7 @@ config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2140000 + default 0x2180000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. -- To view, visit https://review.coreboot.org/c/coreboot/+/57293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a Gerrit-Change-Number: 57293 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: reserve WDT reset reason for debugging
by Patrick Georgi (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57270 ) Change subject: soc/mediatek: reserve WDT reset reason for debugging ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57270/comment/ea38009a_3b2aa829 PS2, Line 10: origional nit: original (in case you edit the commit message to handle Felix's remark) -- To view, visit https://review.coreboot.org/c/coreboot/+/57270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52 Gerrit-Change-Number: 57270 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 19:35:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57299 to look at the new patch set (#4). Change subject: mb/google/volteer: Add type-c port info to coreboot table ...................................................................... mb/google/volteer: Add type-c port info to coreboot table This change adds type-c port information for USB type-c ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 35 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57299/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/57299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Gerrit-Change-Number: 57299 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Move EXTRA_CFLAGS to enable option override
by Patrick Georgi (Code Review) 01 Sep '21

01 Sep '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57181 ) Change subject: libpayload: Move EXTRA_CFLAGS to enable option override ...................................................................... libpayload: Move EXTRA_CFLAGS to enable option override Before this patch EXTRA_CFLAGS were placed before many other options. This made overriding impossible even, when necessary. This patch moves EXTRA_CFLAGS to be placed after original CFLAGS, thus making option overriding possible. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/57181 Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 049b983..90f6b23 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -265,7 +265,7 @@ de$(EMPTY)fine $(1)-objs_$(2)_template $(obj)/$$(1).$(1).o: $$(1).$(2) $(obj)/libpayload-config.h $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" - $(CC) $(3) -MMD $$$$(CFLAGS) -c -o $$$$@ $$$$< + $(CC) $(3) -MMD $$$$(CFLAGS) $(EXTRA_CFLAGS) -c -o $$$$@ $$$$< en$(EMPTY)def end$(EMPTY)if endef diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index fc679dd..a67ba77 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -58,7 +58,7 @@ INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) INCLUDES += -include include/kconfig.h -include include/compiler.h -CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 +CFLAGS += $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla -- To view, visit https://review.coreboot.org/c/coreboot/+/57181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8394b151696eee4bd736d2fb1ad340209e05fbb Gerrit-Change-Number: 57181 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57299 ) Change subject: mb/google/volteer: Add type-c port info to coreboot table ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/57299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5686e5b3dfc6f12aa3f8938f371c14d0b2e490d Gerrit-Change-Number: 57299 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 01 Sep 2021 19:33:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57142 ) Change subject: mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings ...................................................................... mb/goog/brya: Add probed fw_configs to SMBIOS OEM strings Enable this feature, and it can use the probe statement in devicetree to cache of fw_config field as oem string. BUG=b:191931762 TEST=With CBI FW_CONFIG field set to 0x8, set probe AUDIO MAX98390_ALC5682I_I2S_4SPK in devicetree dmidecode -t 11 OEM Strings AUDIO-MAX98390_ALC5682I_I2S_4SPK Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57142 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/mainboard.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 388926f..6287d2c 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -6,6 +6,23 @@ #include <ec/ec.h> #include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <fw_config.h> + +static void add_fw_config_oem_string(const struct fw_config *config, void *arg) +{ + struct smbios_type11 *t; + char buffer[64]; + + t = (struct smbios_type11 *)arg; + + snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name); + t->count = smbios_add_string(t->eos, buffer); +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + fw_config_for_each_found(add_fw_config_oem_string, t); +} void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) { @@ -44,6 +61,7 @@ { dev->ops->init = mainboard_dev_init; dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + dev->ops->get_smbios_strings = mainboard_smbios_strings; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/57142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93cd9ef2d1ad963e66c422cff17b083abf731046 Gerrit-Change-Number: 57142 Gerrit-PatchSet: 5 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/cse: Add argument to send message to appropriate fix...
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Sridhar Siricilla, Aseda Aboagye, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57295 ) Change subject: soc/intel/common/cse: Add argument to send message to appropriate fixed client ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/57295/comment/957449f9_043624cf PS4, Line 7: soc/intel/common/cse: Add argument to send message to appropriate fixed client : : There are multiple HECI clients in the CSE. Currently coreboot is sending : HECI messages to only the MKHI client. Add an argument to heci_send_receive() : funtion to provide flexibility to the caller to select the client for which the : message is intended. : : In the follow-up patches there will be messages sent to one other client. Reflow for 72 characters wide File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/57295/comment/7905cbcf_1be51393 PS4, Line 36: /* This is sent to the MEI client endpoint, not the MKHI endpoint */ : int ret = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MEI_ADDR); : if (!ret) { : printk(BIOS_ERR, "HECI: Failed to send MEI bus disable command!\n"); : return false; : } : : size_t reply_sz = sizeof(reply); : if (!heci_receive(&reply, &reply_sz)) { : printk(BIOS_ERR, "HECI: Failed to receive a reply from CSE\n"); : return false; : } Could adapt this to use the heci_send_receive function now -- To view, visit https://review.coreboot.org/c/coreboot/+/57295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde6d0155b62472b6a7caadc5fc8ea2e2ba6eb0c Gerrit-Change-Number: 57295 Gerrit-PatchSet: 4 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 01 Sep 2021 19:32:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add type-c port info to coreboot table
by Nick Vaccaro (Code Review) 01 Sep '21

01 Sep '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Zhuohao Lee, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57069 to look at the new patch set (#10). Change subject: coreboot tables: Add type-c port info to coreboot table ...................................................................... coreboot tables: Add type-c port info to coreboot table This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-trogdor coreboot' and verify it builds. TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c Passing conn0 type-c info to payload: usb2:9 usb3:1 sbu:0 data:0 Passing conn1 type-c info to payload: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 8 files changed, 166 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/57069/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/57069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Gerrit-Change-Number: 57069 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add argument to send message to appropriate fix...
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

1 0

Change in coreboot[master]: soc/intel/common/cse: Add argument to send message to appropriate fix...
by Tim Wawrzynczak (Code Review) 01 Sep '21

01 Sep '21

1 0

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coreboot-gerrit September 2021