coreboot-gerrit July 2021

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Change in coreboot[master]: Documentation: Improve x86_64
by Patrick Rudolph (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Patrick Rudolph, Arthur Heymans. Patrick Rudolph has uploaded a new patch set (#4) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/56017 ) Change subject: Documentation: Improve x86_64 ...................................................................... Documentation: Improve x86_64 * Move to own markdown document * Better describe current implementation * Update TODOs Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md A Documentation/arch/x86/x86_64.md 2 files changed, 141 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56017/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ba51be629a8c878aad64d3297176457cf8e855 Gerrit-Change-Number: 56017 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/car/core2/cache_as_ram: Add x86_64 support
by Patrick Rudolph (Code Review) 07 Jul '21

07 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45823 ) Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ...................................................................... cpu/intel/car/core2/cache_as_ram: Add x86_64 support Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45823/1 diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 857e039..c75b1e44 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -16,5 +16,13 @@ car_mtrr_mask: .uintptr_t _car_mtrr_mask +car_mtrr_size: +.uintptr_t _car_mtrr_size + car_mtrr_start: .uintptr_t _car_mtrr_start + +#if !CONFIG(NO_XIP_EARLY_STAGES) +xip_mtrr_mask: +.uintptr_t _xip_mtrr_mask +#endif diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..5d6994f 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -6,6 +6,8 @@ .global bootblock_pre_c_entry +#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup: @@ -91,7 +93,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -118,8 +120,8 @@ /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl @@ -133,12 +135,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -156,6 +158,16 @@ andl $0xfffffff0, %esp subl $4, %esp +#if ENV_X86_64 + + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -163,6 +175,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) -- To view, visit https://review.coreboot.org/c/coreboot/+/45823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Gerrit-Change-Number: 45823 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ironlake: Add support for x86_64
by Patrick Rudolph (Code Review) 07 Jul '21

07 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45699 ) Change subject: ironlake: Add support for x86_64 ...................................................................... ironlake: Add support for x86_64 Allow to compile the experimental x86_64 code. Tested on Lenovo Thinkpad T410. Works without issues. Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_2065x/Kconfig M src/cpu/x86/early_reset.S 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45699/1 diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a..5a8b907 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -45,6 +45,7 @@ .section .text .global update_bsp_microcode +.code32 update_bsp_microcode: /* Keep return address */ diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..19eeab0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_2065X +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52..c6d0703 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -9,6 +9,7 @@ .section .text .global check_mtrr +.code32 check_mtrr: /* Use the MTRR default type MSR as a proxy for detecting INIT#. -- To view, visit https://review.coreboot.org/c/coreboot/+/45699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Gerrit-Change-Number: 45699 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Explicitly specify vendor and mainboard
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56079 ) Change subject: configs: Explicitly specify vendor and mainboard ...................................................................... configs: Explicitly specify vendor and mainboard Relying on the implicit defaults for these settings can cause issues in the future. For example, commit 8cc4c5a1e76c0c8aee3a14618c15d38e3bd2bd61 (config.dell_optiplex_9010_sff: Specify board model) was done to prevent a build failure when adding support for other Dell mainboards which make the default board change. Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56079 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support M configs/config.emulation_qemu_aarch64_fit_support_timestamps M configs/config.emulation_qemu_riscv_rv64 M configs/config.emulation_qemu_x86_i440fx_asan M configs/config.emulation_qemu_x86_i440fx_debug M configs/config.emulation_qemu_x86_i440fx_noserial M configs/config.emulation_qemu_x86_i440fx_x86_64 M configs/config.emulation_qemu_x86_q35_smm_tseg M configs/config.facebook_fbg1701.mboot_vboot M configs/config.libretrend_lt1000 M configs/config.ocp_deltalake_cbnt M configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi M configs/config.up_squared.vboot_spi_flash_console 13 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support index 951855e..1727cc7 100644 --- a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support +++ b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support @@ -1,4 +1,5 @@ CONFIG_VENDOR_CAVIUM=y +CONFIG_BOARD_CAVIUM_CN8100_SFF_EVB=y CONFIG_CAVIUM_BDK_VERBOSE_INIT=y CONFIG_CAVIUM_BDK_VERBOSE_DRAM=y CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST=y diff --git a/configs/config.emulation_qemu_aarch64_fit_support_timestamps b/configs/config.emulation_qemu_aarch64_fit_support_timestamps index 7d0054c..2b5234a 100644 --- a/configs/config.emulation_qemu_aarch64_fit_support_timestamps +++ b/configs/config.emulation_qemu_aarch64_fit_support_timestamps @@ -1,3 +1,4 @@ +CONFIG_VENDOR_EMULATION=y CONFIG_COLLECT_TIMESTAMPS=y CONFIG_TIMESTAMPS_ON_CONSOLE=y CONFIG_MAINBOARD_VENDOR="Emulation" diff --git a/configs/config.emulation_qemu_riscv_rv64 b/configs/config.emulation_qemu_riscv_rv64 index d41963c..f5bce48 100644 --- a/configs/config.emulation_qemu_riscv_rv64 +++ b/configs/config.emulation_qemu_riscv_rv64 @@ -1,2 +1,3 @@ +CONFIG_VENDOR_EMULATION=y CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64=y CONFIG_RISCV_OPENSBI=y diff --git a/configs/config.emulation_qemu_x86_i440fx_asan b/configs/config.emulation_qemu_x86_i440fx_asan index a4b504e..3d7f059 100644 --- a/configs/config.emulation_qemu_x86_i440fx_asan +++ b/configs/config.emulation_qemu_x86_i440fx_asan @@ -1 +1,3 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_ASAN=y diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug index e39ff59..85f5499 100644 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ b/configs/config.emulation_qemu_x86_i440fx_debug @@ -1,3 +1,5 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_GDB_STUB=y CONFIG_GDB_WAIT=y CONFIG_FATAL_ASSERTS=y diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial index 2902d02..f71c0ae 100644 --- a/configs/config.emulation_qemu_x86_i440fx_noserial +++ b/configs/config.emulation_qemu_x86_i440fx_noserial @@ -1,3 +1,5 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_POST_IO is not set # CONFIG_POST_DEVICE is not set diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 index d31bbf2..7123646 100644 --- a/configs/config.emulation_qemu_x86_i440fx_x86_64 +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -1 +1,3 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_USE_EXP_X86_64_SUPPORT=y diff --git a/configs/config.emulation_qemu_x86_q35_smm_tseg b/configs/config.emulation_qemu_x86_q35_smm_tseg index 6484c6c..6d64715 100644 --- a/configs/config.emulation_qemu_x86_q35_smm_tseg +++ b/configs/config.emulation_qemu_x86_q35_smm_tseg @@ -1,3 +1,4 @@ +CONFIG_VENDOR_EMULATION=y CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y CONFIG_CPU_QEMU_X86_PARALLEL_MP=y CONFIG_CPU_QEMU_X86_TSEG_SMM=y diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot index 34d349a..08f0c70 100644 --- a/configs/config.facebook_fbg1701.mboot_vboot +++ b/configs/config.facebook_fbg1701.mboot_vboot @@ -1,4 +1,5 @@ CONFIG_VENDOR_FACEBOOK=y +CONFIG_BOARD_FACEBOOK_FBG1701=y CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y diff --git a/configs/config.libretrend_lt1000 b/configs/config.libretrend_lt1000 index 33159f1..0d4f543 100644 --- a/configs/config.libretrend_lt1000 +++ b/configs/config.libretrend_lt1000 @@ -1,4 +1,5 @@ CONFIG_VENDOR_LIBRETREND=y +CONFIG_BOARD_LIBRETREND_LT1000=y CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_TPM2=y diff --git a/configs/config.ocp_deltalake_cbnt b/configs/config.ocp_deltalake_cbnt index 4df1043..4e77566 100644 --- a/configs/config.ocp_deltalake_cbnt +++ b/configs/config.ocp_deltalake_cbnt @@ -1,4 +1,5 @@ CONFIG_VENDOR_OCP=y +CONFIG_BOARD_OCP_DELTALAKE=y CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/intel-sec-tools/testdata/fake_acm/biosacm_cbnt_fake.bin" CONFIG_INTEL_TXT_LOGGING=y CONFIG_INTEL_CBNT_SUPPORT=y diff --git a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi index 09dfbe3..0861af3 100644 --- a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi +++ b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi @@ -8,6 +8,7 @@ # + EM100Pro SPI console # + Debug options CONFIG_VENDOR_PORTWELL=y +CONFIG_BOARD_PORTWELL_M107=y CONFIG_CONSOLE_POST=y # CONFIG_CONSOLE_SERIAL is not set CONFIG_ENABLE_BUILTIN_COM1=y diff --git a/configs/config.up_squared.vboot_spi_flash_console b/configs/config.up_squared.vboot_spi_flash_console index a537035..351e1ca 100644 --- a/configs/config.up_squared.vboot_spi_flash_console +++ b/configs/config.up_squared.vboot_spi_flash_console @@ -1,3 +1,4 @@ CONFIG_VENDOR_UP=y +CONFIG_BOARD_UP_SQUARED=y CONFIG_VBOOT=y CONFIG_CONSOLE_SPI_FLASH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/56079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Gerrit-Change-Number: 56079 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/storo: Update DPTF parameters
by Weimin Wu (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Henry Sun, Tao Xia, Karthik Ramasubramanian. Weimin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56069 ) Change subject: mb/google/dedede/var/storo: Update DPTF parameters ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/56069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Gerrit-Change-Number: 56069 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 05:45:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: spi: Limit the SPI NOR size
by Sajida Bhanu (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Ravi kumar, Julius Werner. Sajida Bhanu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55376 ) Change subject: spi: Limit the SPI NOR size ...................................................................... Patch Set 8: (1 comment) Patchset: PS1: > Yes. Herobrine IDP have SPI size more than 8MB . […] Hi Julius, Herobrine IDP and IDP2 both have SPI-NOR size of 64MB and if we increase romsize to 64MB, we are facing issue in depthcharge as actual heap size is less than 64MB so we are working on it internally, will update the patch soon. Thanks, Sajida -- To view, visit https://review.coreboot.org/c/coreboot/+/55376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Gerrit-Change-Number: 55376 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 04:45:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sajida Bhanu <sbhanu(a)codeaurora.org> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya0: Enable MIPI UFC
by Varshit B Pandya (Code Review) 07 Jul '21

07 Jul '21

Varshit B Pandya has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/55670 ) Change subject: mb/google/brya0: Enable MIPI UFC ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/55670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c Gerrit-Change-Number: 55670 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "mb/google/brya0: Enable MIPI UFC"
by Varshit B Pandya (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: YH Lin, Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, EricR Lai. Hello build bot (Jenkins), YH Lin, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, EricR Lai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56129 to review the following change. Change subject: Revert "mb/google/brya0: Enable MIPI UFC" ...................................................................... Revert "mb/google/brya0: Enable MIPI UFC" This reverts commit bee9d6028edd939acacb48f254ea81ea5077a54d. Reason for revert: Test, Donot merge Change-Id: I369cca6998295e26b585b3448214e4739a896e9f --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 2 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56129/1 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 5bb93e5..0fc782a 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -126,26 +126,7 @@ register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" register "cio2_prt[0]" = "2" - device generic 0 on - # MIPI lanes are split between UFC and WFC depending on - # whether the UFC is USB or MIPI hence probing UFC_USB - probe UFC UFC_USB - end - end - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "2" - register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used - register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" - register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1"" - register "cio2_prt[0]" = "2" - register "cio2_prt[1]" = "1" - device generic 0 on - probe UFC UFC_MIPI_5675 - end + device generic 0 on end end end device ref cnvi_wifi on @@ -420,49 +401,6 @@ register "reg_adv_ctrl20" = "0xf0" device i2c 2C on end end - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM1"" - register "chip_name" = ""Ov 5675 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" - register "ssdb.vcm_type" = "0x0C" - register "vcm_name" = ""VCM0"" - register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" - register "remote_name" = ""IPU0"" - - register "has_power_resource" = "1" - #Controls - register "clk_panel.clks[0].clknum" = "IMGCLKOUT_2" - register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - - register "gpio_panel.gpio[0].gpio_num" = "GPP_C3" #PP3300_FCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_A17" #EN_UCAM_PWR - register "gpio_panel.gpio[2].gpio_num" = "GPP_F20" #reset - - #_ON - register "on_seq.ops_cnt" = "5" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" - - #_OFF - register "off_seq.ops_cnt" = "4" - register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - - device i2c 36 on - probe UFC UFC_MIPI_5675 - end - end end device ref i2c3 on end device ref i2c5 on @@ -600,9 +538,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port6 on - probe UFC UFC_USB - end + device ref usb2_port6 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" -- To view, visit https://review.coreboot.org/c/coreboot/+/56129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I369cca6998295e26b585b3448214e4739a896e9f Gerrit-Change-Number: 56129 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config
by Jamie Chen (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Simon Yang, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55744 ) Change subject: soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392 Gerrit-Change-Number: 55744 Gerrit-PatchSet: 12 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 01:47:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config
by Simon Yang (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Jamie Chen, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55744 to look at the new patch set (#12). Change subject: soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config ...................................................................... soc/intel/jsl: Add DisableExternalVnnVcc1p05BypassMode config This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake. BUG=b:191691430 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392 --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/55744/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/55744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392 Gerrit-Change-Number: 55744 Gerrit-PatchSet: 12 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021