Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55816 )
Change subject: soc/amd/picasso: Allow end range entry for max device ID in IVRS
......................................................................
soc/amd/picasso: Allow end range entry for max device ID in IVRS
Allow hot plug devices to subscribe to IOMMU services. Currently the
IOMMU end range is limited to device B:0 D:1f F:6. This prevents the
devices on bus 1 and higher to subscribe to IOMMU services. As per AMD
IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined,
whether the device ID is actually populated or not. Device entries are
used to report ranges when hot-plug and SR-IOV devices are possible.
With this change the hot plug devices can now bind to IOMMU services
(as tested on kernel v5.4), and below errors are not seen in dmesg.
AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000]
AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000]
AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000]
TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen.
The hot plug devices can successfully bind to IOMMU services in
kernel.
Signed-off-by: Aamir Bohra <aamirbohra(a)gmail.com>
Change-Id: I256c0f8032662674a4d75746de49c250e341c579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Reviewed-by: ritul guru <ritul.bits(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/picasso/agesa_acpi.c
1 file changed, 6 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
Jason Glenesk: Looks good to me, but someone else must approve
ritul guru: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c
index abac9c1..312d5e8 100644
--- a/src/soc/amd/picasso/agesa_acpi.c
+++ b/src/soc/amd/picasso/agesa_acpi.c
@@ -21,6 +21,8 @@
#include <stdlib.h>
#include <arch/mmio.h>
+#define MAX_DEV_ID 0xFFFF
+
unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
{
ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current;
@@ -230,7 +232,7 @@
/* Now repeat all the device entries from type 10h */
current_backup = current;
- current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0);
+ current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0);
ivhd_40->length += (current - current_backup);
root_level = -1;
add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level,
@@ -304,7 +306,7 @@
/* Now repeat all the device entries from type 10h */
current_backup = current;
- current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0);
+ current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0);
ivhd_11->length += (current - current_backup);
root_level = -1;
add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level,
@@ -442,11 +444,11 @@
}
/*
- * Add all possible PCI devices on bus 0 that can generate transactions
+ * Add all possible PCI devices that can generate transactions
* processed by IOMMU. Start with device 00:01.0
*/
current_backup = current;
- current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0);
+ current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0);
ivrs->ivhd.length += (current - current_backup);
root_level = -1;
add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level,
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54734 )
Change subject: src/intel/microcode: Add support for extended signature table
......................................................................
Patch Set 8:
(1 comment)
File src/cpu/intel/microcode/microcode.c:
https://review.coreboot.org/c/coreboot/+/54734/comment/bf3c1dc0_09564013
PS8, Line 139: size_t ext_tbl_len = ucode->total_size - size;
ssize_t could be useful here to avoid overflows.
Especially given that `total_size` can be 0 as the comment below suggests.
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Change subject: Makefile.inc: Drop the cbfs master header from non-X86
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> I'd move this earlier, which should clean up the other commits a fair amount.
Done.
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Change subject: Makefile.inc: Fix IFITTOOL dependencies
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56112/comment/72dbd092_8ddc1d58
PS1, Line 9: somewhere else
> I haven't found a lot of dependencies for IFITTOOL, so maybe better to add it there.
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56119
to look at the new patch set (#3).
Change subject: security/intel/cbnt/Makefile.inc: Improve build flow
......................................................................
security/intel/cbnt/Makefile.inc: Improve build flow
Now that adding all files to cbfs is a distinct Makefile target in the
buildprocess called "add_prebuild_files", it can be used to streamline
setting up cbnt. Using 'files_added::' is not needed any longer.
Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/security/intel/cbnt/Makefile.inc
1 file changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56119/3
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56114
to look at the new patch set (#3).
Change subject: Makefile.inc: Split of image generation in multiple targets
......................................................................
Makefile.inc: Split of image generation in multiple targets
The big '$(obj)/coreboot.pre' target did a lot of things and made the
build process inflexible. Split of much of the functionality in
INTERMEDIATE targets that can have proper dependencies.
Change-Id: If36aee0bd2f75f3941b3bc424a7ec6c775eb1353
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
1 file changed, 29 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/56114/3
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: Makefile.inc: Drop the cbfs master header from non-X86
......................................................................
Makefile.inc: Drop the cbfs master header from non-X86
The pointer to the header has a x86 top mmaped address even though the
boot medium is not mapped that way. If no pointer is used to find the
header FMAP is needed. If FMAP is used anyway there is no need for a
cbfs master header.
Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
1 file changed, 2 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/56120/3
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