coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine
by Cliff Huang (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56006 ) Change subject: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/pmc.c: https://review.coreboot.org/c/coreboot/+/56006/comment/94604500_2b10c129 PS1, Line 126: /* Add Intel Power Engine device */ Please add #if CONFIG(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) here so that we can still build even we don't select the this flag. -- To view, visit https://review.coreboot.org/c/coreboot/+/56006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Gerrit-Change-Number: 56006 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 01:34:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
by Cliff Huang (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56005 ) Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM ...................................................................... Patch Set 1: (6 comments) File src/soc/intel/common/block/acpi/pep.c: https://review.coreboot.org/c/coreboot/+/56005/comment/513b3a10_68f6a590 PS1, Line 120: static void pep_s0ix_enum_functions(void *unused) In general, I don't see Kconfig SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ been used to make pep.c generate or not generate LPM req feature. pep.c is compiled when CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP is set. https://review.coreboot.org/c/coreboot/+/56005/comment/de5060ab_15ba8c1a PS1, Line 143: PMC_IPC_SUBCMD_GEN_COMM_READ, Please see comments in pmc_ipc.h regarding of these two defines, we could just pass 0 for the 2nd argument. https://review.coreboot.org/c/coreboot/+/56005/comment/3544fbc9_2805ea3c PS1, Line 166: pep_s0ix_collect_lpm_requirements, /* Return LPM requirements */ use #if for lpm req. https://review.coreboot.org/c/coreboot/+/56005/comment/a840232a_9f2451e0 PS1, Line 173: DSM_UUID(PEP_S0IX_UUID, pep_s0ix, ARRAY_SIZE(pep_s0ix), NULL), use #if for lpm req. File src/soc/intel/common/block/include/intelblocks/pmc_ipc.h: https://review.coreboot.org/c/coreboot/+/56005/comment/dd4ef1fc_df394c41 PS1, Line 25: #define PMC_IPC_CMD_GENERAL_COMM 0xA0 Please rename to PMC_IPC_CMD_RD_PMC_REG. https://review.coreboot.org/c/coreboot/+/56005/comment/182fcd93_130b83f9 PS1, Line 26: #define PMC_IPC_SUBCMD_GEN_COMM_READ 0x02 When Read PMC reg (0xa0) command is used, there is no subcmd/cmd ID needed. so this define is not required. -- To view, visit https://review.coreboot.org/c/coreboot/+/56005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Gerrit-Change-Number: 56005 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 01:33:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: Move pep.asl to acpigen
by Cliff Huang (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Angel Pons, Patrick Rudolph, Karthik Ramasubramanian. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56004 ) Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/56004/comment/25748aa5_50b92bad PS1, Line 18: config SOC_INTEL_COMMON_BLOCK_ACPI_PEP When this is set, the only change is to include pep.c in the build. Not clear what is the requirement, such as generate_acpi_power_engine() needs to be called at the mainboard. pep.asl is still used for the older platform (included southbridge.asl). One good thing is that we can leave those older platforms intact. But, not having this flag set does not really means that we disable it. Perhaps, just change the name a bit to reflect what it is providing. File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/56004/comment/f902717a_553ad079 PS1, Line 94: void generate_acpi_power_engine(const struct device *dev); Please add #if CONFIG(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) for this declaration. -- To view, visit https://review.coreboot.org/c/coreboot/+/56004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Gerrit-Change-Number: 56004 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 01:23:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Allow end range entry for max device ID in IVRS
by Felix Held (Code Review) 07 Jul '21

07 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55816 ) Change subject: soc/amd/picasso: Allow end range entry for max device ID in IVRS ...................................................................... soc/amd/picasso: Allow end range entry for max device ID in IVRS Allow hot plug devices to subscribe to IOMMU services. Currently the IOMMU end range is limited to device B:0 D:1f F:6. This prevents the devices on bus 1 and higher to subscribe to IOMMU services. As per AMD IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined, whether the device ID is actually populated or not. Device entries are used to report ranges when hot-plug and SR-IOV devices are possible. With this change the hot plug devices can now bind to IOMMU services (as tested on kernel v5.4), and below errors are not seen in dmesg. AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000] TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen. The hot plug devices can successfully bind to IOMMU services in kernel. Signed-off-by: Aamir Bohra <aamirbohra(a)gmail.com> Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/agesa_acpi.c 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve ritul guru: Looks good to me, but someone else must approve diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index abac9c1..312d5e8 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -21,6 +21,8 @@ #include <stdlib.h> #include <arch/mmio.h> +#define MAX_DEV_ID 0xFFFF + unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -230,7 +232,7 @@ /* Now repeat all the device entries from type 10h */ current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); ivhd_40->length += (current - current_backup); root_level = -1; add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, @@ -304,7 +306,7 @@ /* Now repeat all the device entries from type 10h */ current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); ivhd_11->length += (current - current_backup); root_level = -1; add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, @@ -442,11 +444,11 @@ } /* - * Add all possible PCI devices on bus 0 that can generate transactions + * Add all possible PCI devices that can generate transactions * processed by IOMMU. Start with device 00:01.0 */ current_backup = current; - current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), MAX_DEV_ID, 0); ivrs->ivhd.length += (current - current_backup); root_level = -1; add_ivhd_device_entries(NULL, all_devices, 0, -1, &root_level, -- To view, visit https://review.coreboot.org/c/coreboot/+/55816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Gerrit-Change-Number: 55816 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/intel/microcode: Add support for extended signature table
by Nico Huber (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54734 ) Change subject: src/intel/microcode: Add support for extended signature table ...................................................................... Patch Set 8: (1 comment) File src/cpu/intel/microcode/microcode.c: https://review.coreboot.org/c/coreboot/+/54734/comment/bf3c1dc0_09564013 PS8, Line 139: size_t ext_tbl_len = ucode->total_size - size; ssize_t could be useful here to avoid overflows. Especially given that `total_size` can be 0 as the comment below suggests. -- To view, visit https://review.coreboot.org/c/coreboot/+/54734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd Gerrit-Change-Number: 54734 Gerrit-PatchSet: 8 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 20:19:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Avoid NULL pointer deference
by John Zhao (Code Review) 06 Jul '21

06 Jul '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56124 ) Change subject: soc/intel/common: Avoid NULL pointer deference ...................................................................... soc/intel/common: Avoid NULL pointer deference Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458068, 1458070, 1458971, 1458073, 1458075, 1458076 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ib88fa5f44dd33ad1ad2e763d79438b5c5b78acb4 --- M src/soc/intel/common/block/crashlog/crashlog.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56124/1 diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 433545a..c3d0cfd 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -194,8 +194,8 @@ int cl_pmc_re_arm_after_reset(void) { - const struct pmc_ipc_buffer *req = { 0 }; - struct pmc_ipc_buffer *res = NULL; + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; uint32_t cmd_reg; int r; @@ -203,7 +203,7 @@ PMC_IPC_CMD_ID_CRASHLOG_RE_ARM_ON_RESET, PMC_IPC_CMD_SIZE_SHIFT); - r = pmc_send_ipc_cmd(cmd_reg, req, res); + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); if (r < 0) { printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); @@ -217,8 +217,8 @@ /* Sends PMC IPC to clear CrashLog from PMC SSRAM area */ int cl_pmc_clear(void) { - const struct pmc_ipc_buffer *req = { 0 }; - struct pmc_ipc_buffer *res = NULL; + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; uint32_t cmd_reg; int r; @@ -226,7 +226,7 @@ PMC_IPC_CMD_ID_CRASHLOG_ERASE, PMC_IPC_CMD_SIZE_SHIFT); - r = pmc_send_ipc_cmd(cmd_reg, req, res); + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); if (r < 0) { printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); @@ -244,8 +244,8 @@ int cl_pmc_en_gen_on_all_reboot(void) { - const struct pmc_ipc_buffer *req = { 0 }; - struct pmc_ipc_buffer *res = NULL; + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; uint32_t cmd_reg; int r; @@ -253,7 +253,7 @@ PMC_IPC_CMD_ID_CRASHLOG_ON_RESET, PMC_IPC_CMD_SIZE_SHIFT); - r = pmc_send_ipc_cmd(cmd_reg, req, res); + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); if (r < 0) { printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/56124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib88fa5f44dd33ad1ad2e763d79438b5c5b78acb4 Gerrit-Change-Number: 56124 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Avoid NULL pointer deference
by John Zhao (Code Review) 06 Jul '21

06 Jul '21

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56123 ) Change subject: soc/intel/alderlake: Avoid NULL pointer deference ...................................................................... soc/intel/alderlake: Avoid NULL pointer deference Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 --- M src/soc/intel/alderlake/crashlog.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/56123/1 diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index c1eeedf..9435aa0 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -32,8 +32,8 @@ { u32 tmp_bar_addr = 0, desc_table_addr = 0; - const struct pmc_ipc_buffer *req = { 0 }; - struct pmc_ipc_buffer *res = NULL; + const struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer res; uint32_t cmd_reg; int r; @@ -42,13 +42,13 @@ PMC_IPC_CMD_SIZE_SHIFT); printk(BIOS_DEBUG, "cmd_reg from pmc_make_ipc_cmd %d\n", cmd_reg); - r = pmc_send_ipc_cmd(cmd_reg, req, res); + r = pmc_send_ipc_cmd(cmd_reg, &req, &res); if (r < 0) { printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__); return false; } - discovery_buf.val_64_bits = ((u64)res->buf[1] << 32) | res->buf[0]; + discovery_buf.val_64_bits = ((u64)res.buf[1] << 32) | res.buf[0]; if (discovery_buf.bits.supported != 1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Gerrit-Change-Number: 56123 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile.inc: Drop the cbfs master header from non-X86
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Martin Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56120 ) Change subject: Makefile.inc: Drop the cbfs master header from non-X86 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > I'd move this earlier, which should clean up the other commits a fair amount. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/56120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d693bdd4ddaf4c9b3cffb4ea9879c761200aca9 Gerrit-Change-Number: 56120 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 06 Jul 2021 17:22:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Fix IFITTOOL dependencies
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Martin Roth, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56112 ) Change subject: Makefile.inc: Fix IFITTOOL dependencies ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56112/comment/72dbd092_8ddc1d58 PS1, Line 9: somewhere else > I haven't found a lot of dependencies for IFITTOOL, so maybe better to add it there. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c9fc19cca0c72e80d3218dbcc76b89b04feacf Gerrit-Change-Number: 56112 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 17:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Add the x86 bootblock as a regular cbfs file
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Martin Roth. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56122 ) Change subject: Makefile.inc: Add the x86 bootblock as a regular cbfs file ...................................................................... Makefile.inc: Add the x86 bootblock as a regular cbfs file Files of type bootblock are now always top aligned. This assumes only x86 ever uses cbfs file type bootblock. As the cbfs header needs to be at a specific place and it can be updated only later on, use a placeholder cbfs file. Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/arch/x86/Makefile.inc 2 files changed, 27 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56122/1 diff --git a/Makefile.inc b/Makefile.inc index 046f589..7e08a74 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -829,6 +829,7 @@ # CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply # add commands with any additional arguments for cbfstool. # Example: --ext-win-base <base> --ext-win-size <size> +# This top aligns files of type bootblock, assuming that only x86 uses those define cbfs-add-cmd-for-region $(CBFSTOOL) $(obj)/coreboot.pre \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \ @@ -844,6 +845,7 @@ $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ $(call extract_nth,7,$(1)) \ + $(if $(filter bootblock,$(call extract_nth,3,$(1))),-b -$(call file-size, $(call extract_nth,1,$(1)))) \ $(CBFSTOOL_ADD_CMD_OPTIONS) endef @@ -1123,23 +1125,13 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) +# on X86 bootblock is added as a cbfsfile ifneq ($(CONFIG_ARCH_X86),y) $(call add_intermediate, add_bootblock, $(objcbfs)/bootblock.bin) printf " FMAP BOOTBLOCK adding bootblock\n" $(CBFSTOOL) $< write -u \ -r BOOTBLOCK \ -f $(objcbfs)/bootblock.bin -else -$(call add_intermediate, add_bootblock, $(objcbfs)/bootblock.bin) - $(CBFSTOOL) $< add \ - -f $(objcbfs)/bootblock.bin \ - -n bootblock \ - -t bootblock \ - $(TXTIBB) \ - -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ - $(TS_OPTIONS) \ - $(CBFSTOOL_ADD_CMD_OPTIONS) - $(CBFSTOOL) $< add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) endif # ARCH_X86 endif # UPDATE_IMAGE diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3949e3a..ab8f18c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -85,6 +85,30 @@ bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +ifneq ($(CONFIG_UPDATE_IMAGE),y) +# Add a placeholder cbfs file that will be updated later on to hold +# the legacy cbfs master header. +$(obj)/placeholder: + dd if=/dev/zero of=$@ bs=32 count=1 + +cbfs-files-y += cbfs_master_header +cbfs_master_header-file := $(obj)/placeholder +cbfs_master_header-position := 0 +cbfs_master_header-type := "cbfs header" + +$(call add_intermediate, update_master_header, add_prebuild_files) + printf " CBFS Updating master header\n" + rm -f $(obj)/placeholder + $(CBFSTOOL) $< remove -n cbfs_master_header + $(CBFSTOOL) $< add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS) + +endif + +cbfs-files-y += bootblock +bootblock-file := $(objcbfs)/bootblock.bin +bootblock-type := bootblock +bootblock-options := $(TS_OPTIONS) $(TXTIBB) + $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/56122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4de9d7fedf1ae5a37a3310dd42eb07b44c030930 Gerrit-Change-Number: 56122 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021