coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by Subrata Banik (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Paul Menzel, Meera Ravindranath, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... Patch Set 13: (1 comment) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/50996/comment/15a7ea55_f0aca572 PS13, Line 60: ADL_P_DDR5_2 > Here you are skipping the call to `memcfg_init()`. […] @meera, can you please address this review comment ? Consider to move this in below file?https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderla… void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { static const int spd_array[] = { 0xA0, 0xA2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xA4, 0xA6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } switch (mb_cfg->type) { case MEM_TYPE_DDR5: /* Fill FSP UPDs with SMBus Addresses until SMbus driver in coreboot is updated with DDR5 support TODO: Drop this check once the SMBus driver is ready */ for (int i = 0; i < 16; i++) m_cfg->SpdAddressTable[i] = spd_array[i]; case MEM_TYPE_DDR4: meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; break; .... } that way you are not skipping anything important? -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 13 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 10:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Paul Menzel (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Daniel Kurtz, Kevin Chang, Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... Patch Set 2: (3 comments) File src/mainboard/google/kahlee/variants/treeya/audio.c: https://review.coreboot.org/c/coreboot/+/56100/comment/c775406c_7d75411b PS2, Line 22: 0xfedc2000 Can you define a macro for this? https://review.coreboot.org/c/coreboot/+/56100/comment/9187f9cb_f4a648f9 PS2, Line 24: } Can one of the checks be moved into the do-while condition? ``` do { mmio_dev = dev_find_path(mmio_dev, DEVICE_PATH_MMIO); if (mmio_dev == NULL) break; } while (mmio_dev->path.mmio.addr != 0xfedc2000); ``` https://review.coreboot.org/c/coreboot/+/56100/comment/ca9ca20c_25c3d9e8 PS2, Line 27: return; Can’t you return already above? Maybe also print an error? -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 09:48:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: spi: Limit the SPI NOR size
by Paul Menzel (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Ravi kumar, Julius Werner. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55376 ) Change subject: spi: Limit the SPI NOR size ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55376/comment/9be65ac6_5977824d PS8, Line 10: lLimiting limiting -- To view, visit https://review.coreboot.org/c/coreboot/+/55376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Gerrit-Change-Number: 55376 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 09:41:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/galtic: Add charger throttling function
by Paul Menzel (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Henry Sun, Frank Chu, Sumeet R Pawnikar, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54673 ) Change subject: mb/google/dedede/var/galtic: Add charger throttling function ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54673/comment/718e68d6_e158c6e7 PS5, Line 10: Please document, where you got the values from. -- To view, visit https://review.coreboot.org/c/coreboot/+/54673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e1849551ff051bca591f19f9e40da4c89ab74e7 Gerrit-Change-Number: 54673 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 09:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: adjust telemetry settings
by Edward O'Callaghan (Code Review) 07 Jul '21

07 Jul '21

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56077 ) Change subject: mb/google/zork/var/shuboz: adjust telemetry settings ...................................................................... mb/google/zork/var/shuboz: adjust telemetry settings According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30595 -> 30400 VDD Offset: 77 -> 317 SOC Slope : 24063 -> 23789 SOC Offset: 105 -> 94 BUG=b:190338440 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Sam McNally <sammc(a)google.com> Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Daniel Kurtz: Looks good to me, approved Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved Sam McNally: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 459b3ce..c3cc9e6 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -18,10 +18,10 @@ # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope_mA" = "30595" - register "telemetry_vddcr_vdd_offset" = "77" - register "telemetry_vddcr_soc_slope_mA" = "24063" - register "telemetry_vddcr_soc_offset" = "105" + register "telemetry_vddcr_vdd_slope_mA" = "30400" + register "telemetry_vddcr_vdd_offset" = "317" + register "telemetry_vddcr_soc_slope_mA" = "23789" + register "telemetry_vddcr_soc_offset" = "94" # USB OC pin mapping -- To view, visit https://review.coreboot.org/c/coreboot/+/56077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef Gerrit-Change-Number: 56077 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Randy Wang <ifanw(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block/acpi: Move pep.asl to acpigen
by Angel Pons (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Cliff Huang, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Angel Pons, Patrick Rudolph, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56004 ) Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/acpi/Kconfig: https://review.coreboot.org/c/coreboot/+/56004/comment/4257bdd9_89866568 PS1, Line 18: config SOC_INTEL_COMMON_BLOCK_ACPI_PEP > When this is set, the only change is to include pep.c in the build. […] I'm not sure if I follow. Do you mean that the current Kconfig option's name can lead to confusion with the unrelated pep.asl file? File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/56004/comment/2dccce0e_b3298182 PS1, Line 94: void generate_acpi_power_engine(const struct device *dev); > Please add #if CONFIG(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) for this declaration. No. Please never guard function declarations with preprocessor. Otherwise, all calls also need to be guarded with preprocessor, which is very ugly: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP) generate_acpi_power_engine(dev); #endif Instead, leave the declaration as-is, and guard the calls with a regular C if statement: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) generate_acpi_power_engine(dev); This can be compiled regardless of the state of `SOC_INTEL_COMMON_BLOCK_ACPI_PEP`. However, if the condition is true but `generate_acpi_power_engine()` is not defined, the linker will complain about "undefined symbol" (the function), which results in a build failure. When the condition is false, the compiler optimises out (removes) the call to `generate_acpi_power_engine()`, so the linker never "sees" it, and building succeeds (assuming there aren't any other issues, of course). -- To view, visit https://review.coreboot.org/c/coreboot/+/56004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Gerrit-Change-Number: 56004 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 08:54:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Save resume vector to stack in x86_64 mode
by Arthur Heymans (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Patrick Rudolph, Iru Cai, Iru Cai (vimacs). Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55947 ) Change subject: arch/x86: Save resume vector to stack in x86_64 mode ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Gerrit-Change-Number: 55947 Gerrit-PatchSet: 4 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 07:37:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Save resume vector to stack in x86_64 mode
by Iru Cai (vimacs) (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Patrick Rudolph, Iru Cai, Iru Cai (vimacs). Hello build bot (Jenkins), Patrick Rudolph, Paul Menzel, Arthur Heymans, Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55947 to look at the new patch set (#4). Change subject: arch/x86: Save resume vector to stack in x86_64 mode ...................................................................... arch/x86: Save resume vector to stack in x86_64 mode In x86_64, the first function parameter is passed in rdi register, and the 32-bit code after exiting long mode reads the resume vector in 4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp). Also note that the function attribute "regparm" only works on x86-32 targets according to the GCC manual, so "asmlinkage" doesn't change the ABI of an x86_64 function. Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64 mode after this change. Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/arch/x86/wakeup.S 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/55947/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252 Gerrit-Change-Number: 55947 Gerrit-PatchSet: 4 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/cbfstool: Catch baseaddress parameter errors early
by build bot (Jenkins) (Code Review) 07 Jul '21

07 Jul '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56127 ) Change subject: util/cbfstool: Catch baseaddress parameter errors early ...................................................................... Patch Set 1: (3 comments) File util/cbfstool/cbfstool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123549): https://review.coreboot.org/c/coreboot/+/56127/comment/fe5b5a82_fffc681b PS1, Line 811: ERROR("Wrong -b parameter: FSP non-XIP has to be located outside of flash\n"); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123549): https://review.coreboot.org/c/coreboot/+/56127/comment/686bbb83_7e6ef1bd PS1, Line 817: ERROR("Wrong -b parameter: base not mapped inside flash\n"); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123549): https://review.coreboot.org/c/coreboot/+/56127/comment/8ec9c59c_7ce25d5a PS1, Line 822: ERROR("Wrong -b parameter: base bigger than %s region\n", line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/56127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfd121b34ce79fe1394f79d5cbd4da6ddf5c5656 Gerrit-Change-Number: 56127 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 07:08:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement report_cache_info() function
by Subrata Banik (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55654 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Implement report_cache_info() function ...................................................................... soc/intel/alderlake: Implement report_cache_info() function Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: CPU: Genuine Intel(R) 0000 CPU: ID 906a0, Alderlake Platform, ucode: 00000019 CPU: AES supported, TXT supported, VT supported Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache: Size 0xc00000 bytes Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/bootblock/report_platform.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/55654/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Gerrit-Change-Number: 55654 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021