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Change subject: spi: Limit the SPI NOR size
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55376/comment/9be65ac6_5977824d
PS8, Line 10: lLimiting
limiting
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Change subject: mb/google/dedede/var/galtic: Add charger throttling function
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54673/comment/718e68d6_e158c6e7
PS5, Line 10:
Please document, where you got the values from.
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Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/common/block/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/56004/comment/4257bdd9_89866568
PS1, Line 18: config SOC_INTEL_COMMON_BLOCK_ACPI_PEP
> When this is set, the only change is to include pep.c in the build. […]
I'm not sure if I follow. Do you mean that the current Kconfig option's name can lead to confusion with the unrelated pep.asl file?
File src/soc/intel/common/block/include/intelblocks/acpi.h:
https://review.coreboot.org/c/coreboot/+/56004/comment/2dccce0e_b3298182
PS1, Line 94: void generate_acpi_power_engine(const struct device *dev);
> Please add #if CONFIG(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) for this declaration.
No. Please never guard function declarations with preprocessor. Otherwise, all calls also need to be guarded with preprocessor, which is very ugly:
#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)
generate_acpi_power_engine(dev);
#endif
Instead, leave the declaration as-is, and guard the calls with a regular C if statement:
if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
generate_acpi_power_engine(dev);
This can be compiled regardless of the state of `SOC_INTEL_COMMON_BLOCK_ACPI_PEP`. However, if the condition is true but `generate_acpi_power_engine()` is not defined, the linker will complain about "undefined symbol" (the function), which results in a build failure.
When the condition is false, the compiler optimises out (removes) the call to `generate_acpi_power_engine()`, so the linker never "sees" it, and building succeeds (assuming there aren't any other issues, of course).
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Change subject: arch/x86: Save resume vector to stack in x86_64 mode
......................................................................
Patch Set 4: Code-Review+2
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Change subject: arch/x86: Save resume vector to stack in x86_64 mode
......................................................................
arch/x86: Save resume vector to stack in x86_64 mode
In x86_64, the first function parameter is passed in rdi register, and
the 32-bit code after exiting long mode reads the resume vector in
4(%esp), so it's needed to save the resume vector from rdi to 4(%rsp).
Also note that the function attribute "regparm" only works on x86-32
targets according to the GCC manual, so "asmlinkage" doesn't change
the ABI of an x86_64 function.
Tested on HP EliteBook 2560p. The laptop can resume from S3 in x86_64
mode after this change.
Change-Id: I45f2678071b2511c0af5dce9d9b73ac70dfd7252
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M src/arch/x86/wakeup.S
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/55947/4
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Change subject: util/cbfstool: Catch baseaddress parameter errors early
......................................................................
Patch Set 1:
(3 comments)
File util/cbfstool/cbfstool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123549):
https://review.coreboot.org/c/coreboot/+/56127/comment/fe5b5a82_fffc681b
PS1, Line 811: ERROR("Wrong -b parameter: FSP non-XIP has to be located outside of flash\n");
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123549):
https://review.coreboot.org/c/coreboot/+/56127/comment/686bbb83_7e6ef1bd
PS1, Line 817: ERROR("Wrong -b parameter: base not mapped inside flash\n");
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123549):
https://review.coreboot.org/c/coreboot/+/56127/comment/8ec9c59c_7ce25d5a
PS1, Line 822: ERROR("Wrong -b parameter: base bigger than %s region\n",
line over 96 characters
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Change subject: soc/intel/alderlake: Implement report_cache_info() function
......................................................................
soc/intel/alderlake: Implement report_cache_info() function
Make use of deterministic cache helper functions from Alder Lake
SoC code to print useful information during boot as below:
CPU: Genuine Intel(R) 0000
CPU: ID 906a0, Alderlake Platform, ucode: 00000019
CPU: AES supported, TXT supported, VT supported
Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384
Cache: Size 0xc00000 bytes
Change-Id: I30a56266015d69abccb885b3f230689488ee0360
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/alderlake/bootblock/report_platform.c
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/55654/4
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Change subject: arch/x86: Helper functions to get deterministic cache parameters
......................................................................
arch/x86: Helper functions to get deterministic cache parameters
This patch creates helper function that internally detects the CPU
type (AMD or Intel) and pick the leaf to send CPUID instruction with
different cache level to retrieve deterministic cache parameters.
Lists of helper functions generated as part of this CL :
1. cpu_check_deterministic_cache_cpuid_supported => if CPU has support
for deterministic cache using CPUID instruction.
2. cpu_get_cache_ways_assoc_info => Get cache ways for associativity.
3. cpu_get_cache_type => Get cache type.
4. cpu_get_cache_level => Get cache level.
5. cpu_get_cache_phy_partition_info => Get cache physical partitions.
6. cpu_get_cache_line_size => Get cahce line size.
7. cpu_get_cache_sets => Get cache number of sets.
8. cpu_is_cache_full_assoc => Check if cache is fully associative.
9. cpu_get_max_cache_share => Cores are sharing this cache.
10. get_cache_size => Calculate the cache size.
Change-Id: I0dd701fb47460092448b64c7fa2162f762bf3095
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/arch/x86/cpu_common.c
M src/arch/x86/include/arch/cpu.h
2 files changed, 204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55965/4
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Change subject: Documentation: Improve x86_64
......................................................................
Patch Set 4: Code-Review+2
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