coreboot-gerrit July 2021

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Change in coreboot[master]: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56105 ) Change subject: vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability ...................................................................... vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stability Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56105 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index 71415d2..b761473 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -33,7 +33,7 @@ u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733 DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION {LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE}, -- To view, visit https://review.coreboot.org/c/coreboot/+/56105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707 Gerrit-Change-Number: 56105 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/mediatek/mt8195: Improve settings of duty calibration
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56104 ) Change subject: vc/mediatek/mt8195: Improve settings of duty calibration ...................................................................... vc/mediatek/mt8195: Improve settings of duty calibration Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c M src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h 2 files changed, 18 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index cea83a0..16f16ff 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -14804,18 +14804,26 @@ #endif #endif { + U8 u1ChannelIdx; + U8 u1backup_channel = vGetPHY2ChannelMapping(p); + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if(p->femmc_Ready==1) { - DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); - DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); - #if __LP5_COMBO__ - WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]); - #endif - #if APPLY_DQDQM_DUTY_CALIBRATION - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); - #endif + for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){ + vSetPHY2ChannelMapping(p, u1ChannelIdx); + + DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); + DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); + #if __LP5_COMBO__ + WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]); + #endif + #if APPLY_DQDQM_DUTY_CALIBRATION + DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); + DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); + #endif + } + vSetPHY2ChannelMapping(p, u1backup_channel); vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K); return; diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h index a40f290..d27d7ea 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h @@ -123,7 +123,7 @@ #else #define ENABLE_EYESCAN_GRAPH 1 #endif -#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 +#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 #define EYESCAN_GRAPH_RX_VREF_STEP 2 #define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/56104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda Gerrit-Change-Number: 56104 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Add dramc_param.h
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56098 ) Change subject: soc/mediatek/mt8195: Add dramc_param.h ...................................................................... soc/mediatek/mt8195: Add dramc_param.h The dramc_param.h defines the header version, structure and APIs for the DRAM calibration parameters stored on the flash, and should be platform independent. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- R src/soc/mediatek/mt8192/include/soc/dramc_param.h C src/soc/mediatek/mt8195/include/soc/dramc_param.h 2 files changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h similarity index 96% rename from src/soc/mediatek/common/include/soc/dramc_param.h rename to src/soc/mediatek/mt8192/include/soc/dramc_param.h index 7794a73..7d6efda 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__ -#define __SOC_MEDIATEK_DRAMC_PARAM_H__ +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ /* * NOTE: This file is shared between coreboot and dram blob. Any change in this @@ -149,4 +149,4 @@ int validate_dramc_param(const void *blob); int is_valid_dramc_param(const void *blob); int initialize_dramc_param(void *blob); -#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */ +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h similarity index 95% copy from src/soc/mediatek/common/include/soc/dramc_param.h copy to src/soc/mediatek/mt8195/include/soc/dramc_param.h index 7794a73..0e1b62c 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__ -#define __SOC_MEDIATEK_DRAMC_PARAM_H__ +#ifndef __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ /* * NOTE: This file is shared between coreboot and dram blob. Any change in this @@ -12,7 +12,7 @@ #include <sys/types.h> #include <soc/dramc_soc.h> -#define DRAMC_PARAM_HEADER_VERSION 6 +#define DRAMC_PARAM_HEADER_VERSION 7 enum DRAMC_PARAM_STATUS_CODES { DRAMC_SUCCESS = 0, @@ -149,4 +149,4 @@ int validate_dramc_param(const void *blob); int is_valid_dramc_param(const void *blob); int initialize_dramc_param(void *blob); -#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */ +#endif /* __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Gerrit-Change-Number: 56098 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Enable DCM
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56097 ) Change subject: soc/mediatek/mt8195: Enable DCM ...................................................................... soc/mediatek/mt8195: Enable DCM Enable DCM settings on the MT8195 platform. DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Signed-off-by: Garmin Chang <garmin.chang(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56097 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/include/soc/pll.h M src/soc/mediatek/mt8195/pll.c 2 files changed, 62 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h index cc133c8..9b6f314f6 100644 --- a/src/soc/mediatek/mt8195/include/soc/pll.h +++ b/src/soc/mediatek/mt8195/include/soc/pll.h @@ -580,4 +580,45 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x10 << 5) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x1f << 5) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31), +}; + #endif /* SOC_MEDIATEK_MT8195_PLL_H */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index fc16535..ebdc37f 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -713,6 +713,27 @@ setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21); setbits32(&mt8195_infracfg_ao_bcrm->vdnr_dcm_top_infra_ctrl0, 0x2); + /* dcm_infracfg_ao_aximem_bus_dcm */ + clrsetbits32(&mt8195_infracfg_ao->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_infra_bus_dcm */ + clrsetbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_infra_rx_p2p_dcm */ + clrsetbits32(&mt8195_infracfg_ao->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + /* dcm_infracfg_ao_peri_bus_dcm */ + clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, + INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_peri_module_dcm */ + clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); -- To view, visit https://review.coreboot.org/c/coreboot/+/56097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Gerrit-Change-Number: 56097 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56074/comment/d5d6aee4_e914922f PS5, Line 309: s_cfg->UsbTcPortEn = 0; : for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { : /* TCSS xHCI --> Root Hub --> Type-C Port */ : const struct device_path port_path[] = { : {.type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_TCSS_XHCI}, : {.type = DEVICE_PATH_USB, .usb.port_type = 0, .usb.port_id = 0}, : {.type = DEVICE_PATH_USB, .usb.port_type = 3, .usb.port_id = i} }; : const struct device *port = find_dev_nested_path(pci_root_bus(), port_path, : ARRAY_SIZE(port_path)); : : if (is_dev_enabled(port)) : s_cfg->UsbTcPortEn |= BIT(i); : } right here 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 5 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 14:43:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/bsd/future: Introduce future API
by Angel Pons (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Raul Rangel, Aaron Durbin, Furquan Shaikh, Marshall Dawson, Julius Werner, Eric Peers. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56047 ) Change subject: commonlib/bsd/future: Introduce future API ...................................................................... Patch Set 1: (3 comments) File src/commonlib/bsd/include/commonlib/bsd/future.h: https://review.coreboot.org/c/coreboot/+/56047/comment/b3b63fef_6e408ecc PS1, Line 1: /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ > curious - why did this go in bsd? Why not? https://review.coreboot.org/c/coreboot/+/56047/comment/611e60ae_4834100e PS1, Line 59: !! nit: redundant, return value already does this conversion https://review.coreboot.org/c/coreboot/+/56047/comment/9b41ccdc_6a09bee7 PS1, Line 83: nit: one space too many -- To view, visit https://review.coreboot.org/c/coreboot/+/56047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I125a946233f122c2848704296efbcb3ca3c96079 Gerrit-Change-Number: 56047 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 14:43:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: CB:55361 is already setting UsbTcPortEn... I verified it on Brya: ``` diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5b0d63108b14..ac55ba9d00b1 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -307,6 +307,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { + printk(BIOS_INFO, "@@ TDW looking for usb3 port id %d: ", i); /* TCSS xHCI --> Root Hub --> Type-C Port */ const struct device_path port_path[] = { {.type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_TCSS_XHCI}, @@ -315,9 +316,15 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, const struct device *port = find_dev_nested_path(pci_root_bus(), port_path, ARRAY_SIZE(port_path)); - if (is_dev_enabled(port)) + if (is_dev_enabled(port)) { + printk(BIOS_INFO, "Found!\n"); s_cfg->UsbTcPortEn |= BIT(i); + } else { + printk(BIOS_INFO, "Non-existent or disabled\n"); + } } + + printk(BIOS_INFO, "@@ TDW UsbTcPortEn = 0x%x\n", s_cfg->UsbTcPortEn); } ``` ``` @@ TDW looking for usb3 port id 0: Found! @@ TDW looking for usb3 port id 1: Found! @@ TDW looking for usb3 port id 2: Found! @@ TDW looking for usb3 port id 3: Non-existent or disabled @@ TDW UsbTcPortEn = 0x7 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 5 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 14:42:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Modify Wifi-SAR sku condition
by Karthik Ramasubramanian (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Henry Sun, Stanley Wu, Paul Fagerburg, Melo Chuang. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55112 ) Change subject: mb/google/dedede/var/boten: Modify Wifi-SAR sku condition ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/dedede/variants/boten/variant.c: https://review.coreboot.org/c/coreboot/+/55112/comment/ac7b5857_b466e880 PS1, Line 33: if (sku_id >= SKU_ID_BOTENFLEX) > there should be always needing a Wifi SAR table, so that's why we modify the conditional expressions […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Gerrit-Change-Number: 55112 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 14:42:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/storo: Update DPTF parameters
by Karthik Ramasubramanian (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Henry Sun, Tao Xia. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56069 ) Change subject: mb/google/dedede/var/storo: Update DPTF parameters ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Gerrit-Change-Number: 56069 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 14:28:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Configure I2C times for touchpad
by Karthik Ramasubramanian (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Henry Sun, Tao Xia. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56016 ) Change subject: mb/google/dedede/var/sasukette: Configure I2C times for touchpad ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Not for this change. But would recommend to configure the rise and fall times in a follow-up change. -- To view, visit https://review.coreboot.org/c/coreboot/+/56016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Gerrit-Change-Number: 56016 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rui Huang <huangrui(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 14:27:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021