coreboot-gerrit July 2021

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by EricR Lai (Code Review) 07 Jul '21

07 Jul '21

EricR Lai has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Abandoned duplicate -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 5 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock
by Subrata Banik (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56152 ) Change subject: soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock ...................................................................... soc/intel/alderlake: Call cpu_fill_code_cache() from bootblock Make use of cpu_fill_code_cache() helper function to perform cache stress test. TEST=This function perform cache stress test if SOC_INTEL_CAR_DEBUG is selected. Change-Id: If0708737ce000eddd8d36876d195712d63c3915e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/56152/1 diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index b8086a4..cc08921 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -25,6 +26,7 @@ void bootblock_soc_init(void) { + cpu_fill_code_cache(); report_platform_info(); bootblock_pch_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/56152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0708737ce000eddd8d36876d195712d63c3915e Gerrit-Change-Number: 56152 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr: Add check_var_mtrr_range_enabled() helper function
by Subrata Banik (Code Review) 07 Jul '21

07 Jul '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56151 ) Change subject: cpu/x86/mtrr: Add check_var_mtrr_range_enabled() helper function ...................................................................... cpu/x86/mtrr: Add check_var_mtrr_range_enabled() helper function This patch creates a helper function to verify if a given address range is belogs to variable MTRRs. check_var_mtrr_range_enabled() function performs this check to know if the given address range is cacheable. Change-Id: I0df698c1501ad678ec0d58e133d7e437b658f4ca Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/mtrr.h 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56151/1 diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index aa301d0..2cd9428 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -132,3 +132,53 @@ { return var_mtrr_set_with_cb(ctx, addr, size, type, set_mtrr); } + +static bool get_var_mtrr_range(int index, uintptr_t *base_address, size_t *length) +{ + bool ret = false; + uint32_t address_bits; + uint64_t address_mask; + const uint32_t msr_reg = MTRR_PHYS_BASE(index); + uint64_t mask; + union { + uint64_t u64; + msr_t s; + } msr_a; + union { + uint64_t u64; + msr_t s; + } msr_m; + + address_bits = cpu_phys_address_size(); + address_mask = (1ULL << address_bits) - 1; + + msr_a.s = rdmsr(msr_reg); + msr_m.s = rdmsr(msr_reg + 1); + if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { + *base_address = (msr_a.u64 & 0xfffffffffffff000ULL) + & address_mask; + + mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; + *length = (~mask & address_mask) + 1; + ret = true; + } + return ret; +} + +bool check_var_mtrr_range_enabled(uintptr_t base, size_t size) +{ + uintptr_t base_address; + size_t length; + bool ret = false; + int variable_mtrrs_cnt = get_var_mtrr_count(); + for (int i = 0; i < variable_mtrrs_cnt; i++) { + if (get_var_mtrr_range(i, &base_address, &length)) { + if (base_address == base && length == size) { + ret = true; + break; + } + } + } + + return ret; +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index b8d1517..097e0ea 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -96,6 +96,8 @@ /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void); +/* Function to check if a given address range is belongs to variable MTRRs */ +bool check_var_mtrr_range_enabled(uintptr_t base, size_t size); /* Insert a temporary MTRR range for the duration of coreboot's runtime. * This function needs to be called after the first MTRR solution is derived. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0df698c1501ad678ec0d58e133d7e437b658f4ca Gerrit-Change-Number: 56151 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [Don't merge] soc/intel/alderlake: Test Code to enable SOC_INTEL_CAR_...
by Subrata Banik (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55655 to look at the new patch set (#3). Change subject: [Don't merge] soc/intel/alderlake: Test Code to enable SOC_INTEL_CAR_DEBUG ...................................................................... [Don't merge] soc/intel/alderlake: Test Code to enable SOC_INTEL_CAR_DEBUG Change-Id: I5f012b9d8b56b3d5ebb7cd24461af4d779913a20 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/55655/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f012b9d8b56b3d5ebb7cd24461af4d779913a20 Gerrit-Change-Number: 55655 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add cpu_fill_code_cache() to test eNEM
by Subrata Banik (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55653 to look at the new patch set (#3). Change subject: soc/intel/common: Add cpu_fill_code_cache() to test eNEM ...................................................................... soc/intel/common: Add cpu_fill_code_cache() to test eNEM This patch creates a common API to perform stess test by doing a memcpy between memory region into CAR. The idea here is to fill the cache lines and make sure eNEM could able to replace code lines without any hang. If available cache size itself is higher than code size then skip running this function. Also, SoC user can select SOC_INTEL_CAR_DEBUG Kconfig to debug any CAR related issues. TEST=Run this function on ADL-P RVP and don't see any hang. Change-Id: Ieb1e644f154b8f8d8da41ba8084e99827e7eff23 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 3 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/55653/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb1e644f154b8f8d8da41ba8084e99827e7eff23 Gerrit-Change-Number: 55653 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/boten: Modify Wifi-SAR sku condition
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55112 ) Change subject: mb/google/dedede/var/boten: Modify Wifi-SAR sku condition ...................................................................... mb/google/dedede/var/boten: Modify Wifi-SAR sku condition Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR detect condition for boten/botenflex sku. BUG=b:186174768 TEST=build and test on boten/botenflex Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55112 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/boten/variant.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c index 9afcb27..584ddb6d 100644 --- a/src/mainboard/google/dedede/variants/boten/variant.c +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -30,7 +30,7 @@ { uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id == SKU_ID_BOTENFLEX) + if (sku_id >= SKU_ID_BOTENFLEX) return "wifi_sar-botenflex.hex"; return "wifi_sar-boten.hex"; -- To view, visit https://review.coreboot.org/c/coreboot/+/55112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Gerrit-Change-Number: 55112 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/storo: Update DPTF parameters
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56069 ) Change subject: mb/google/dedede/var/storo: Update DPTF parameters ...................................................................... mb/google/dedede/var/storo: Update DPTF parameters Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 7ddadbd..e824652 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -77,16 +77,16 @@ .tdp_pl2_override = 20, }" - register "tcc_offset" = "5" # TCC of 100C + register "tcc_offset" = "10" # TCC of 95C device domain 0 on device pci 04.0 on chip drivers/intel/dptf ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 3000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 60, 3000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 60, 3000),}" + [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 67, 3000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 67, 3000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 67, 3000),}" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), -- To view, visit https://review.coreboot.org/c/coreboot/+/56069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Gerrit-Change-Number: 56069 Gerrit-PatchSet: 2 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Configure I2C times for touchpad
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56016 ) Change subject: mb/google/dedede/var/sasukette: Configure I2C times for touchpad ...................................................................... mb/google/dedede/var/sasukette: Configure I2C times for touchpad Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390.4 kHz BUG=b:192601250 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56016 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/sasukette/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index a39b9d1..776ba8a 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -23,8 +23,8 @@ .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 185, - .scl_hcnt = 95, + .scl_lcnt = 180, + .scl_hcnt = 90, .sda_hold = 40, } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/56016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1603a48a3e841b6a50aa0c703697ec615b2854 Gerrit-Change-Number: 56016 Gerrit-PatchSet: 2 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rui Huang <huangrui(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56035 ) Change subject: mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap ...................................................................... mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and provide a flashmap for partitioning. Select the used flashmap on variant level to allow different layouts for different variants. Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56035 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig A src/mainboard/siemens/mc_ehl/mc_ehl.fmd A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig 3 files changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index 63b153b..035bc85 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -1,7 +1,7 @@ config BOARD_SIEMENS_BASEBOARD_MC_EHL def_bool n select SOC_INTEL_ELKHARTLAKE - select BOARD_ROMSIZE_KB_32768 + select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select HAVE_SPD_IN_CBFS select HAVE_ACPI_TABLES diff --git a/src/mainboard/siemens/mc_ehl/mc_ehl.fmd b/src/mainboard/siemens/mc_ehl/mc_ehl.fmd new file mode 100644 index 0000000..78faf2b --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/mc_ehl.fmd @@ -0,0 +1,11 @@ +FLASH @0xff000000 CONFIG_ROM_SIZE { + SI_ALL 0x400000 { + SI_DESC 0x1000 + SI_ME 0x3ff000 + } + SI_BIOS 0xc00000 { + FMAP 0x200 + RW_MRC_CACHE 0x10000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig new file mode 100644 index 0000000..b6e2b33 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig @@ -0,0 +1,7 @@ +if BOARD_SIEMENS_MC_EHL1 + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" + +endif # BOARD_SIEMENS_MC_EHL1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Gerrit-Change-Number: 56035 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl: Clean up Kconfig
by Patrick Georgi (Code Review) 07 Jul '21

07 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56034 ) Change subject: mb/siemens/mc_ehl: Clean up Kconfig ...................................................................... mb/siemens/mc_ehl: Clean up Kconfig Remove Kconfig switches that are not needed for mc_ehl based mainboards. Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56034 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig 1 file changed, 5 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index b5a5a90..63b153b 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -1,16 +1,11 @@ config BOARD_SIEMENS_BASEBOARD_MC_EHL def_bool n - select BOARD_ROMSIZE_KB_32768 - select DRIVERS_I2C_HID - select DRIVERS_INTEL_DPTF - select DRIVERS_I2C_GENERIC - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EC_ACPI - select HAVE_SPD_IN_CBFS - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES select SOC_INTEL_ELKHARTLAKE + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_TABLES + source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig" @@ -36,10 +31,6 @@ int default 512 -config VBOOT - select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 - config UART_FOR_CONSOLE int default 2 if INTEL_LPSS_UART_FOR_CONSOLE -- To view, visit https://review.coreboot.org/c/coreboot/+/56034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If231f37f06c6763d52a821799e87fdb3010af0aa Gerrit-Change-Number: 56034 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021