coreboot-gerrit June 2021

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 13: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120645): https://review.coreboot.org/c/coreboot/+/55128/comment/7e186374_b93f66d9 PS13, Line 115: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:06:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/bc1a9a6e_2c34d5af PS1, Line 210: pci_dev_read_resources > You mean the root port itself? On Intel platforms at least, the root ports are described in ACPI (\_ […] No, the root port is handled by the AMD PCIe GPP driver. I mean the actual NVMe device node. i.e., \_SB.PCI0.GP00.XXXX The current form of this driver handles writing the device node, but using the `target` method it's not clear who writes the ACPI node. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:04:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

1 0

Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Sean Rhodes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 13: Code-Review+2 (1 comment) File Documentation/mainboard/starlabs/labtop.md: https://review.coreboot.org/c/coreboot/+/55128/comment/0123d34a_f39be2dc PS9, Line 1: # Star Labs LabTop : : ## Specs : : - CPU (full processor specs available at https://ark.intel.com) : - Intel i7-10710U (Comet Lake) : - Intel i3-10110U (Comet Lake) : - Intel i7-8550u (Kaby Lake Refresh) : - EC : - ITE IT8987E : - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys : - Battery : - Charger, using AC adapter or USB-C PD : - Suspend / resume : - GPU : - Intel UHD Graphics 620 : - GOP driver is recommended, VBT is provided : - eDP 13-inch 1920x1080 LCD : - HDMI video : - USB-C DisplayPort video : - Memory : - 16GB on-board for Comet Lake platforms[^1] : - 8GB on-board for Kaby Lake Refresh platform. : - Networking : - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) : - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) : - Sound : - Realtek ALC256 : - Internal speakers : - Internal microphone : - Combined headphone / microphone 3.5-mm jack : - HDMI audio : - USB-C DisplayPort audio : - Storage : - M.2 PCIe SSD : - RTS5129 MicroSD card reader : - USB : - 1280x720 CCD camera : - USB 3.1 Gen 2 Type-C (left) : - USB 3.1 Gen 2 Type-A (left) : - USB 3.1 Gen 1 Type-A (right) : : [^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` : : ## Building coreboot : : ### Preliminaries : : Prior to building coreboot the following files are required: : : Comet Lake and Kaby Lake configurations: : - Intel Flash Descriptor file (descriptor.bin) : - Intel Management Engine firmware (me.bin) : : Comet Lake configuration only: : - ITE IT8987E firmware (it8987-x.xx.bin) : : All Star Labs platforms: : - Splash screen image in Windows 3.1 BMP format (Logo.bmp) : : These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. : : ### Build : : The following commands will build a working image: : : ##### LabTop Mk IV (Comet Lake) : : ```bash : make distclean : make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml : make : ``` : : ##### LabTop Mk III (Kaby Lake) : : ```bash : make distclean : make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl : make : ``` : : ## Flashing coreboot : : ```eval_rst : +---------------------+------------+ : | Type | Value | : +=====================+============+ : | Socketed flash | no | : +---------------------+------------+ : | Vendor | Winbond | : +---------------------+------------+ : | Model | 25Q128JVSQ | : +---------------------+------------+ : | Size | 16 MiB | : +---------------------+------------+ : | Package | SOIC-8 | : +---------------------+------------+ : | Internal flashing | yes | : +---------------------+------------+ : | External flashing | no | : +---------------------+------------+ > That's the last time I used the GUI! Haha, I never used it before 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:01:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Sean Rhodes (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 13: (1 comment) File Documentation/mainboard/starlabs/labtop.md: https://review.coreboot.org/c/coreboot/+/55128/comment/a705f613_f79ffc87 PS9, Line 1: # Star Labs LabTop : : ## Specs : : - CPU (full processor specs available at https://ark.intel.com) : - Intel i7-10710U (Comet Lake) : - Intel i3-10110U (Comet Lake) : - Intel i7-8550u (Kaby Lake Refresh) : - EC : - ITE IT8987E : - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys : - Battery : - Charger, using AC adapter or USB-C PD : - Suspend / resume : - GPU : - Intel UHD Graphics 620 : - GOP driver is recommended, VBT is provided : - eDP 13-inch 1920x1080 LCD : - HDMI video : - USB-C DisplayPort video : - Memory : - 16GB on-board for Comet Lake platforms[^1] : - 8GB on-board for Kaby Lake Refresh platform. : - Networking : - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) : - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) : - Sound : - Realtek ALC256 : - Internal speakers : - Internal microphone : - Combined headphone / microphone 3.5-mm jack : - HDMI audio : - USB-C DisplayPort audio : - Storage : - M.2 PCIe SSD : - RTS5129 MicroSD card reader : - USB : - 1280x720 CCD camera : - USB 3.1 Gen 2 Type-C (left) : - USB 3.1 Gen 2 Type-A (left) : - USB 3.1 Gen 1 Type-A (right) : : [^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` : : ## Building coreboot : : ### Preliminaries : : Prior to building coreboot the following files are required: : : Comet Lake and Kaby Lake configurations: : - Intel Flash Descriptor file (descriptor.bin) : - Intel Management Engine firmware (me.bin) : : Comet Lake configuration only: : - ITE IT8987E firmware (it8987-x.xx.bin) : : All Star Labs platforms: : - Splash screen image in Windows 3.1 BMP format (Logo.bmp) : : These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. : : ### Build : : The following commands will build a working image: : : ##### LabTop Mk IV (Comet Lake) : : ```bash : make distclean : make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml : make : ``` : : ##### LabTop Mk III (Kaby Lake) : : ```bash : make distclean : make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl : make : ``` : : ## Flashing coreboot : : ```eval_rst : +---------------------+------------+ : | Type | Value | : +=====================+============+ : | Socketed flash | no | : +---------------------+------------+ : | Vendor | Winbond | : +---------------------+------------+ : | Model | 25Q128JVSQ | : +---------------------+------------+ : | Size | 16 MiB | : +---------------------+------------+ : | Package | SOIC-8 | : +---------------------+------------+ : | Internal flashing | yes | : +---------------------+------------+ : | External flashing | no | : +---------------------+------------+ > some reason you removed this? That's the last time I used the GUI! -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add support for 2 new DRAM parts
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54951 ) Change subject: mb/google/brya: Add support for 2 new DRAM parts ...................................................................... mb/google/brya: Add support for 2 new DRAM parts 1) Hynix H9HCNNNCPMMLXR-NEE 2) Micron MT53E1G32D2NP-046 WT:B BUG=b:186616388, b:181736400 Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54951 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/brya0/memory/Makefile.inc M src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt 3 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc index 79605c2..aed901a 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/brya0/memory/Makefile.inc @@ -5,3 +5,4 @@ SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += lp4x-spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 3(0b0011) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B diff --git a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt index d926626..025a5b6 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/dram_id.generated.txt @@ -3,3 +3,5 @@ H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) MT53E2G32D4NQ-046 WT:A 2 (0010) +H9HCNNNCPMMLXR-NEE 3 (0011) +MT53E1G32D2NP-046 WT:B 3 (0011) diff --git a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt index 178c17d..c8a24cc 100644 --- a/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt +++ b/src/mainboard/google/brya/variants/brya0/memory/mem_list_variant.txt @@ -2,3 +2,5 @@ H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A MT53E2G32D4NQ-046 WT:A +H9HCNNNCPMMLXR-NEE +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/54951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfe8aa4f8d8aab2011fa8d17b3b2c8659658e3 Gerrit-Change-Number: 54951 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add new memory parts for ADL boards
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54950 ) Change subject: soc/intel/alderlake: Add new memory parts for ADL boards ...................................................................... soc/intel/alderlake: Add new memory parts for ADL boards Use currently global_lp4x_mem_parts.json.txt to regenerate SPD files for LP4x memory parts that can be used with ADL-based mainboards. BUG=b:186616388 Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54950 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt index 347118d..bb15c0c 100644 --- a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt @@ -3,6 +3,7 @@ K4U6E3S4AA-MGCL,lp4x-spd-1.hex K4UBE3D4AA-MGCL,lp4x-spd-3.hex MT53E1G32D2NP-046 WT:A,lp4x-spd-4.hex +MT53E1G32D2NP-046 WT:B,lp4x-spd-3.hex H9HKNNNCRMBVAR-NEH,lp4x-spd-1.hex MT53E1G64D4SQ-046 WT:A,lp4x-spd-4.hex MT53E512M32D2NP-046 WT:F,lp4x-spd-1.hex @@ -20,3 +21,4 @@ NT6AP256T32AV-J1,lp4x-spd-6.hex MT53E1G32D4NQ-046 WT:E,lp4x-spd-3.hex MT53E2G32D4NQ-046 WT:A,lp4x-spd-7.hex +MT53E512M32D1NP-046 WT:B,lp4x-spd-1.hex -- To view, visit https://review.coreboot.org/c/coreboot/+/54950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Gerrit-Change-Number: 54950 Gerrit-PatchSet: 6 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55000 ) Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config ...................................................................... util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index d032064..8df4472 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -68,7 +68,7 @@ "channelsPerDie": 2, "diesPerPackage": 2, "bitWidthPerChannel": 16, - "ranksPerChannel": 1, + "ranksPerChannel": 2, "speedMbps": 4267 } }, -- To view, visit https://review.coreboot.org/c/coreboot/+/55000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Gerrit-Change-Number: 55000 Gerrit-PatchSet: 6 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/d50fd558_c69a9256 PS1, Line 210: pci_dev_read_resources > What about the NVMe case where we don't have a PCI driver that writes the ACPI node? […] You mean the root port itself? On Intel platforms at least, the root ports are described in ACPI (\_SB.PCI0.RPxx), so it's perfectly valid to open up the scope (the RP device is in the DSDT). That's how the current intel/common/pcie3/rtd3 driver works, it uses the RP device itself (plus the weird "PXSX" device) -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:50:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2021