coreboot-gerrit June 2021

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/cded111f_fde07438 PS1, Line 210: pci_dev_read_resources > I would just write into that device's scope, regardless. […] What about the NVMe case where we don't have a PCI driver that writes the ACPI node? device ref gpp_bridge_3 on device pci 00.0 alias nvme on end # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device use nvme as target register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_40)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "1" device generic 0 on end end end # NVMe In this case we never write a PCI ACPI Device node. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:42:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Sean Rhodes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 12: Code-Review+2 (1 comment) File Documentation/mainboard/starlabs/labtop.md: https://review.coreboot.org/c/coreboot/+/55128/comment/c01b1299_4638fbc4 PS9, Line 1: # Star Labs LabTop : : ## Specs : : - CPU (full processor specs available at https://ark.intel.com) : - Intel i7-10710U (Comet Lake) : - Intel i3-10110U (Comet Lake) : - Intel i7-8550u (Kaby Lake Refresh) : - EC : - ITE IT8987E : - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys : - Battery : - Charger, using AC adapter or USB-C PD : - Suspend / resume : - GPU : - Intel UHD Graphics 620 : - GOP driver is recommended, VBT is provided : - eDP 13-inch 1920x1080 LCD : - HDMI video : - USB-C DisplayPort video : - Memory : - 16GB on-board for Comet Lake platforms[^1] : - 8GB on-board for Kaby Lake Refresh platform. : - Networking : - AX201 CNVi WiFi / Bluetooth soldered to PCBA (Comet Lake) : - 8265 PCIe WiFi / Bluetooth soldered to PCBA (Kaby Lake Refresh) : - Sound : - Realtek ALC256 : - Internal speakers : - Internal microphone : - Combined headphone / microphone 3.5-mm jack : - HDMI audio : - USB-C DisplayPort audio : - Storage : - M.2 PCIe SSD : - RTS5129 MicroSD card reader : - USB : - 1280x720 CCD camera : - USB 3.1 Gen 2 Type-C (left) : - USB 3.1 Gen 2 Type-A (left) : - USB 3.1 Gen 1 Type-A (right) : : [^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` : : ## Building coreboot : : ### Preliminaries : : Prior to building coreboot the following files are required: : : Comet Lake and Kaby Lake configurations: : - Intel Flash Descriptor file (descriptor.bin) : - Intel Management Engine firmware (me.bin) : : Comet Lake configuration only: : - ITE IT8987E firmware (it8987-x.xx.bin) : : All Star Labs platforms: : - Splash screen image in Windows 3.1 BMP format (Logo.bmp) : : These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. : : ### Build : : The following commands will build a working image: : : ##### LabTop Mk IV (Comet Lake) : : ```bash : make distclean : make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml : make : ``` : : ##### LabTop Mk III (Kaby Lake) : : ```bash : make distclean : make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl : make : ``` : : ## Flashing coreboot : : ```eval_rst : +---------------------+------------+ : | Type | Value | : +=====================+============+ : | Socketed flash | no | : +---------------------+------------+ : | Vendor | Winbond | : +---------------------+------------+ : | Model | 25Q128JVSQ | : +---------------------+------------+ : | Size | 16 MiB | : +---------------------+------------+ : | Package | SOIC-8 | : +---------------------+------------+ : | Internal flashing | yes | : +---------------------+------------+ : | External flashing | no | : +---------------------+------------+ some reason you removed this? -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:35:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/d1a351a0_b1fc1e9a PS1, Line 210: pci_dev_read_resources > > Also, if the drivers/pcie/rtd3/ is supposed to be any kind of PCIe device, then it might have to s […] I would just write into that device's scope, regardless. As long as the `target` device is enabled, then it will get written into the SSDT as well. Order of definition isn't important in the tables. I *think* you could open the scope (which hasn't been defined yet) and OSPM is smart enough to figure it out. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:32:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/e1a9e587_d3400387 PS1, Line 210: pci_dev_read_resources > Also, if the drivers/pcie/rtd3/ is supposed to be any kind of PCIe device, then it might have to support all the operations including pci_rom* operations too. So if rtd3 needs to generate the node it gets a little tricky for cases like this: device ref gpp_bridge_0 on chip drivers/wifi/generic register "wake" = "GEVENT_8" device pci 00.0 alias wifi on end end # Test so the Wifi can be placed into D3 chip drivers/pcie/rtd3/device use wifi as target register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_5)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_29)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "1" device generic 0 on end end end # WLAN The wifi/generic driver handles creating the ACPI Device, so rtd3 can't create a duplicate device. Should I make the rtd3 driver check if config->target->ops->acpi_fill_ssdt == NULL, and then generate the PCI ACPI node, otherwise just write into the device scope? -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cezanne/psp_verstage: add reset/timer svc
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55137 ) Change subject: cezanne/psp_verstage: add reset/timer svc ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Gerrit-Change-Number: 55137 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:22:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: initialize i2c in soc_init
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Kangheui Won, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55136 ) Change subject: psp_verstage: initialize i2c in soc_init ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Gerrit-Change-Number: 55136 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:21:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Sean Rhodes (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 12: (2 comments) File Documentation/mainboard/starlabs/labtop.md: https://review.coreboot.org/c/coreboot/+/55128/comment/2086b7de_47ae2093 PS9, Line 120: higher than **1.5.6** will work. : ![fwupd version](https://cdn.shopify.com/s/files/1/2059/5897/files/fwupdV.png?v=161… : On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: : > sounds like you mean 1.5. […] Done File src/mainboard/starlabs/labtop/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/55128/comment/f1807a96_985991d2 PS9, Line 55: > Sorry I mean there's a tab between #define and EC_GPE_SWI, should be a space Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:20:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 12: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120638): https://review.coreboot.org/c/coreboot/+/55128/comment/90d07191_bc2800ba PS12, Line 115: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 12 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:20:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 11: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120637): https://review.coreboot.org/c/coreboot/+/55128/comment/4ddaf923_116003a8 PS11, Line 115: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:15:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: move MIPI camera setting into overridetree
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55134 ) Change subject: mb/google/brya: move MIPI camera setting into overridetree ...................................................................... mb/google/brya: move MIPI camera setting into overridetree In order to support no MIPI camera variant, move related configuration into variant folder. BUG=b:188272162 BRANCH=none TEST=build no MIPI camera variant without error Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 83 insertions(+), 86 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index ddb1ece..36635fb 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -129,19 +129,6 @@ device domain 0 on device ref igpu on end device ref dtt on end - device ref ipu on - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used - register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" - register "cio2_prt[0]" = "2" - device generic 0 on end - end - end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp2 on end @@ -156,78 +143,6 @@ device generic 0 on end end end - - device ref i2c0 on - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI8856"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 8856 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - - register "ssdb.lanes_used" = "4" - register "ssdb.link_used" = "0" - register "ssdb.vcm_type" = "0x0C" - register "vcm_name" = ""VCM0"" - register "num_freq_entries" = "2" - register "link_freq[0]" = "360 * MHz" # 360 MHz - register "link_freq[1]" = "180 * MHz" # 180 MHz - register "remote_name" = ""IPU0"" - - register "has_power_resource" = "1" - #Controls - register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" - register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - - register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 - register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 - register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset - - #_ON - register "on_seq.ops_cnt" = "5" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" - - #_OFF - register "off_seq.ops_cnt" = "4" - register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - - device i2c 10 on end - end - chip drivers/intel/mipi_camera - register "acpi_uid" = "2" - register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW9768 VCM"" - register "device_type" = "INTEL_ACPI_CAMERA_VCM" - - register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" - register "vcm_compat" = ""dongwoon,dw9768"" - - device i2c 0C on end - end - chip drivers/intel/mipi_camera - register "acpi_uid" = "1" - register "acpi_name" = ""NVM0"" - register "chip_name" = ""AT24 EEPROM"" - register "device_type" = "INTEL_ACPI_CAMERA_NVM" - - register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" - register "nvm_compat" = ""atmel,24c1024"" - - register "nvm_size" = "0x2800" - register "nvm_pagesize" = "0x01" - register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" - - device i2c 58 on end - end - end #I2C0 device ref i2c3 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 452e1d8..78fc472 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -116,6 +116,19 @@ device generic 0 on end end end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -146,7 +159,76 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360 * MHz" # 360 MHz + register "link_freq[1]" = "180 * MHz" # 180 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + device i2c 58 on end + end + end #I2C0 device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" -- To view, visit https://review.coreboot.org/c/coreboot/+/55134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Gerrit-Change-Number: 55134 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: merged

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coreboot-gerrit June 2021