June 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: arch/x86: Set RTC century byte offset in FADT x86-wide
by Werner Zeh (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Hello Arthur Heymans, build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55012 to look at the new patch set (#2). Change subject: arch/x86: Set RTC century byte offset in FADT x86-wide ...................................................................... arch/x86: Set RTC century byte offset in FADT x86-wide The century byte of the year is stored in CMOS at offset 0x32 for all x86 platforms (done by MC146818 RTC code which is default enabled for x86). This location is not fixed per definition but is established during the past years as 'de facto' standard. This offset is passed into the OS via the ACPI FADT where e.g. Linux uses it if it is set to something != 0. Currently this byte is set differently on all the platforms, either to 0x32 or to 0x0 or even to nothing which results in 0x0. Since this is architecture specific and valid for all the platforms, set this century byte once in the architecture specific code. Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/skylake/fadt.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 23 files changed, 2 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/55012/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Gerrit-Change-Number: 55012 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Furquan Shaikh (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54966/comment/36225f44_9f346535 PS1, Line 9: I decided : to copy and modify it because the Intel driver has a lot of Intel : specific code. > 2. So this is where I grew uncomfortable. I'm not sure of the sequence required to put a PCIe Root Port into D3. We also don't currently support hot plugging support while the root port is in D0. I'm not sure what it would take to support hot plugging while in D3, or if it's even supported by the hardware. The AMD CRB doesn't implement any of this. I think it is the same for Intel platforms too. At least from a hardware design standpoint, we haven't designed these ports for being hot plug capable. But, looks like it was required for the GL9755 SD express device. We can skip this for AMD platforms if you want to wait until it is really required. It would be good to at least track this somehow in case AMD platforms use the same device and run into similar issues. > So I think the Intel driver conflates the two power resources. Your explanation about the two power resources for the root port and the downstream device makes sense. File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/ddb5e287_ee5128cf PS1, Line 210: pci_dev_read_resources > I wasn't a fan of the fake device because it made it difficult to understand. The reasons for the fake/generic device under SoC internal devices have been: 1. Reuse the device/pci* support, scan/enumeration and the device_operations without having to copy the device_operations structure and related function calls in each of these device drivers. 2. Keep the organization in devicetree consistent i.e. the SoC internal devices are never surrounded by any special chip driver. example: drivers/intel/ish, drivers/wifi/generic, soc/intel/common/block/pcie/rtd. > It was confusing why it was writing `acpigen_write_ADR(0);` for the `PXSX`, but then I realized it was the PCI Address of the first device/function on the root port. I think that is primarily to satisfy the assumption in the kernel driver about having a PXSX device. It is not really anything to do with the fake/generic device in coreboot devicetree. > Thoughts? You mentioned that the bridge case can be ignored for now. Though that is fine, I think the problem with duplicating PCI device_operations(i.e. duplicating default_pci_ops_dev) in different device drivers is that it scatters the PCI generic operation structures in different places which can make it difficult to track and perform common changes/fixes. Also, if the drivers/pcie/rtd3/ is supposed to be any kind of PCIe device, then it might have to support all the operations including pci_rom* operations too. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 04:36:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Werner Zeh (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Kyösti Mälkki. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/55088/comment/b366e88b_f13fcc9e PS2, Line 834: Now check if there are more speed settings available and report them as well. > Would it be bad to expose information about all different I2C speeds to the OS? We can skip the ones […] The reason I took this approach is that I would like to avoid invalid values being reported. With the current patch only the timings, that a mainboard explicitly provides in addition to the used one will be reported. This means that the developer needs to be active to add these additional timings where we have a higher chance that they are valid or even were measured to assure their validity. If we apply a generic set of timings, chances are way higher that there will bu "dummy" timings not matching the real hardware very soon. -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 04:29:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X series
by Bill XIE (Code Review) June 1, 2021

June 1, 2021

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55111 ) Change subject: mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X series ...................................................................... mb/asus/p8x7x-series: Add P8H77-V as a variant of P8X7X series Mainboard information can be found in the included documentation. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72 --- A Documentation/mainboard/asus/p8h77-v.jpg A Documentation/mainboard/asus/p8h77-v.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8h77-v/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8h77-v/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8h77-v/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8h77-v/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb 13 files changed, 577 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/55111/1 diff --git a/Documentation/mainboard/asus/p8h77-v.jpg b/Documentation/mainboard/asus/p8h77-v.jpg new file mode 100644 index 0000000..6fe8545 --- /dev/null +++ b/Documentation/mainboard/asus/p8h77-v.jpg Binary files differ diff --git a/Documentation/mainboard/asus/p8h77-v.md b/Documentation/mainboard/asus/p8h77-v.md new file mode 100644 index 0000000..97b84ea --- /dev/null +++ b/Documentation/mainboard/asus/p8h77-v.md @@ -0,0 +1,81 @@ +# ASUS P8Z77-V + +This page describes how to run coreboot on the [ASUS P8H77-V]. + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | no | ++---------------------+----------------+ +``` + +The flash IC is located beside the SATA ports (circled): +![](p8z77-v.jpg) + +### How to flash + +The main SPI flash cannot be written because the vendor firmware disables BIOSWE +and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external +programmer is required. You must flash standalone, flashing in-circuit doesn't +work. The flash chip is socketed, so it's easy to remove and reflash. + +## Working + +- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28 +- Integrated Ethernet NIC +- S3 Suspend to RAM +- USB2 on rear and front panel connectors +- USB3 +- Integrated SATA +- CPU Temp sensors (tested PSensor on GNU/Linux) +- Native raminit +- Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working) +- PCIe in PCIe-16x slots +- Debug output from serial port + +## Untested + +- EHCI debugging +- S/PDIF audio +- PS/2 mouse + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8H77-V]: https://www.asus.com/supportonly/p8h77v/helpdesk_knowledge/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index 190a0a2..ca223d2 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -24,12 +24,14 @@ default "p8z77-m_pro" if BOARD_ASUS_P8Z77_M_PRO default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V + default "p8h77-v" if BOARD_ASUS_P8H77_V config MAINBOARD_PART_NUMBER string default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V + default "P8H77-V" if BOARD_ASUS_P8H77_V config OVERRIDE_DEVICETREE string diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index ec37df2..dbb60e6 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -23,3 +23,11 @@ select MAINBOARD_USES_IFD_GBE_REGION select SUPERIO_NUVOTON_NCT6779D select USE_NATIVE_RAMINIT + + +config BOARD_ASUS_P8H77_V + bool "P8H77-V" + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/board_info.txt new file mode 100644 index 0000000..f9c8e6d --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/p8h77v/helpdesk_knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default new file mode 100644 index 0000000..c7aa620 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout new file mode 100644 index 0000000..0f9de5e --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/cmos.layout @@ -0,0 +1,86 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/data.vbt new file mode 100644 index 0000000..2aa53a1 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c new file mode 100644 index 0000000..87508a7 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/gma-mainboard.ads new file mode 100644 index 0000000..e6b0407 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/gpio.c new file mode 100644 index 0000000..e180958 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/gpio.c @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c new file mode 100644 index 0000000..f246af7 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11060397, /* Codec Vendor / Device ID: VIA VT1708S */ + 0x1043836c, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1043836c), + AZALIA_PIN_CFG(0, 0x19, 0x01011012), + AZALIA_PIN_CFG(0, 0x1a, 0x01a19036), + AZALIA_PIN_CFG(0, 0x1b, 0x0181303e), + AZALIA_PIN_CFG(0, 0x1c, 0x01014010), + AZALIA_PIN_CFG(0, 0x1d, 0x0221401f), + AZALIA_PIN_CFG(0, 0x1e, 0x02a19038), + AZALIA_PIN_CFG(0, 0x1f, 0x503701f0), + AZALIA_PIN_CFG(0, 0x20, 0x185600f0), + AZALIA_PIN_CFG(0, 0x21, 0x074521f0), + AZALIA_PIN_CFG(0, 0x22, 0x01016011), + AZALIA_PIN_CFG(0, 0x23, 0x01012014), + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb new file mode 100644 index 0000000..f20b49c --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -0,0 +1,65 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + chip southbridge/intel/bd82x6x + register "gen1_dec" = "0x000c0291" + device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) + device pci 1c.1 off end # RP #2: + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: AR8161 GbE NIC + device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge + device pci 1c.6 on end # RP #7: PCIEX1_1 + device pci 1c.7 on end # RP #8: PCIEX1_2 + + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on # GPIO0 + drq 0xe0 = 0x7f + drq 0xe1 = 0x80 + drq 0xf0 = 0xfe + end + device pnp 2e.9 off end # GPIO8 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 on end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 on end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR Wake-up + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # Port 80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/55111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72 Gerrit-Change-Number: 55111 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/asus: Rename p8z77-series to p8x7x-series
by Bill XIE (Code Review) June 1, 2021

June 1, 2021

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55110 ) Change subject: mb/asus: Rename p8z77-series to p8x7x-series ...................................................................... mb/asus: Rename p8z77-series to p8x7x-series Much more asus boards using Panther Point PCH other than Z77 can fit into this series. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I3e0b5734658912a69ccde94d530399059502c4c4 --- R src/mainboard/asus/p8x7x-series/Kconfig R src/mainboard/asus/p8x7x-series/Kconfig.name R src/mainboard/asus/p8x7x-series/Makefile.inc R src/mainboard/asus/p8x7x-series/acpi/ec.asl R src/mainboard/asus/p8x7x-series/acpi/platform.asl R src/mainboard/asus/p8x7x-series/acpi/superio.asl R src/mainboard/asus/p8x7x-series/board_info.txt R src/mainboard/asus/p8x7x-series/devicetree.cb R src/mainboard/asus/p8x7x-series/dsdt.asl R src/mainboard/asus/p8x7x-series/hda_verb.c R src/mainboard/asus/p8x7x-series/mainboard.c R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/board_info.txt R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.default R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/cmos.layout R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/data.vbt R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/gma-mainboard.ads R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/gpio.c R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c R src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb R src/mainboard/asus/p8x7x-series/variants/p8z77-v/board_info.txt R src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.default R src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout R src/mainboard/asus/p8x7x-series/variants/p8z77-v/data.vbt R src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c R src/mainboard/asus/p8x7x-series/variants/p8z77-v/gma-mainboard.ads R src/mainboard/asus/p8x7x-series/variants/p8z77-v/gpio.c R src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c R src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/board_info.txt R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.default R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.layout R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/data.vbt R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gpio.c R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c R src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 38 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/55110/1 diff --git a/src/mainboard/asus/p8z77-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig similarity index 92% rename from src/mainboard/asus/p8z77-series/Kconfig rename to src/mainboard/asus/p8x7x-series/Kconfig index da0814a..190a0a2 100644 --- a/src/mainboard/asus/p8z77-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -config BOARD_ASUS_P8Z77_SERIES +config BOARD_ASUS_P8X7X_SERIES bool select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -13,11 +13,11 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 -if BOARD_ASUS_P8Z77_SERIES +if BOARD_ASUS_P8X7X_SERIES config MAINBOARD_DIR string - default "asus/p8z77-series" + default "asus/p8x7x-series" config VARIANT_DIR string diff --git a/src/mainboard/asus/p8z77-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name similarity index 86% rename from src/mainboard/asus/p8z77-series/Kconfig.name rename to src/mainboard/asus/p8x7x-series/Kconfig.name index a61b82d..ec37df2 100644 --- a/src/mainboard/asus/p8z77-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -1,6 +1,6 @@ config BOARD_ASUS_P8Z77_M_PRO bool "P8Z77-M PRO" - select BOARD_ASUS_P8Z77_SERIES + select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA select MAINBOARD_HAS_LPC_TPM @@ -8,7 +8,7 @@ config BOARD_ASUS_P8Z77_V_LX2 bool "P8Z77-V LX2" - select BOARD_ASUS_P8Z77_SERIES + select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select REALTEK_8168_RESET select SUPERIO_NUVOTON_NCT6779D @@ -16,7 +16,7 @@ config BOARD_ASUS_P8Z77_V bool "P8Z77-V" - select BOARD_ASUS_P8Z77_SERIES + select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select DRIVERS_ASMEDIA_ASPM_BLACKLIST # for ASM1061 eSATA select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/asus/p8z77-series/Makefile.inc b/src/mainboard/asus/p8x7x-series/Makefile.inc similarity index 100% rename from src/mainboard/asus/p8z77-series/Makefile.inc rename to src/mainboard/asus/p8x7x-series/Makefile.inc diff --git a/src/mainboard/asus/p8z77-series/acpi/ec.asl b/src/mainboard/asus/p8x7x-series/acpi/ec.asl similarity index 100% rename from src/mainboard/asus/p8z77-series/acpi/ec.asl rename to src/mainboard/asus/p8x7x-series/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-series/acpi/platform.asl b/src/mainboard/asus/p8x7x-series/acpi/platform.asl similarity index 100% rename from src/mainboard/asus/p8z77-series/acpi/platform.asl rename to src/mainboard/asus/p8x7x-series/acpi/platform.asl diff --git a/src/mainboard/asus/p8z77-series/acpi/superio.asl b/src/mainboard/asus/p8x7x-series/acpi/superio.asl similarity index 100% rename from src/mainboard/asus/p8z77-series/acpi/superio.asl rename to src/mainboard/asus/p8x7x-series/acpi/superio.asl diff --git a/src/mainboard/asus/p8z77-series/board_info.txt b/src/mainboard/asus/p8x7x-series/board_info.txt similarity index 100% rename from src/mainboard/asus/p8z77-series/board_info.txt rename to src/mainboard/asus/p8x7x-series/board_info.txt diff --git a/src/mainboard/asus/p8z77-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb similarity index 100% rename from src/mainboard/asus/p8z77-series/devicetree.cb rename to src/mainboard/asus/p8x7x-series/devicetree.cb diff --git a/src/mainboard/asus/p8z77-series/dsdt.asl b/src/mainboard/asus/p8x7x-series/dsdt.asl similarity index 100% rename from src/mainboard/asus/p8z77-series/dsdt.asl rename to src/mainboard/asus/p8x7x-series/dsdt.asl diff --git a/src/mainboard/asus/p8z77-series/hda_verb.c b/src/mainboard/asus/p8x7x-series/hda_verb.c similarity index 100% rename from src/mainboard/asus/p8z77-series/hda_verb.c rename to src/mainboard/asus/p8x7x-series/hda_verb.c diff --git a/src/mainboard/asus/p8z77-series/mainboard.c b/src/mainboard/asus/p8x7x-series/mainboard.c similarity index 100% rename from src/mainboard/asus/p8z77-series/mainboard.c rename to src/mainboard/asus/p8x7x-series/mainboard.c diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/board_info.txt similarity index 100% rename from src/mainboard/asus/p8z77-series/variants/p8z77-m_pro/board_info.txt rename to src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/board_info.txt diff --git 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rename from src/mainboard/asus/p8z77-series/variants/p8z77-v/hda_verb.c rename to src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb similarity index 100% rename from src/mainboard/asus/p8z77-series/variants/p8z77-v/overridetree.cb rename to src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/board_info.txt similarity index 100% rename from src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/board_info.txt rename to src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/board_info.txt diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/cmos.default similarity index 100% rename from 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src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/hda_verb.c rename to src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb similarity index 100% rename from src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb rename to src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/55110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e0b5734658912a69ccde94d530399059502c4c4 Gerrit-Change-Number: 55110 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: rename acpi_soc_fill_bert and add return value
by Lance Zhao (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55053 ) Change subject: acpi: rename acpi_soc_fill_bert and add return value ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaa3eed51645e1b3bc904c6279d171e3a10d59be Gerrit-Change-Number: 55053 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 02:49:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: rework BERT SSDT generation logic
by Lance Zhao (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Francois Toguo Fotso, Tim Wawrzynczak, Patrick Rudolph, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55054 ) Change subject: acpi: rework BERT SSDT generation logic ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a281f5f636010ba3b2e7e097e9cf53683022aea Gerrit-Change-Number: 55054 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 02:48:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: drop unused parameter from acpi_soc_fill_bert
by Lance Zhao (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, Felix Held. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55052 ) Change subject: acpi: drop unused parameter from acpi_soc_fill_bert ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Gerrit-Change-Number: 55052 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 02:32:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/storo: Modify I2C times for touchpad
by zanxi chen (Code Review) June 1, 2021

June 1, 2021

zanxi chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55109 ) Change subject: mb/google/dedede/var/storo: Modify I2C times for touchpad ...................................................................... mb/google/dedede/var/storo: Modify I2C times for touchpad Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately (380<frequency<400 kHz). Measured touchpad I2C frequency is 394 kHz BUG=b:189740533 BRANCH=dedede TEST=Build bios and make sure frequency meets specification. Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/55109/1 diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 40b17df..6336192 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -26,8 +26,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 125, - .fall_time_ns = 19, + .rise_time_ns = 260, + .fall_time_ns = 50, }, .i2c[1] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/55109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Gerrit-Change-Number: 55109 Gerrit-PatchSet: 1 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi/device: Add ability to generate proper _STA for PowerResource
by Lance Zhao (Code Review) June 1, 2021

June 1, 2021

Attention is currently required from: Raul Rangel, Furquan Shaikh, Tim Wawrzynczak. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55027 ) Change subject: acpi/device: Add ability to generate proper _STA for PowerResource ...................................................................... Patch Set 2: (1 comment) File src/include/acpi/acpi_device.h: https://review.coreboot.org/c/coreboot/+/55027/comment/773395a2_fbb2c3da PS2, Line 459: : /* Write a _STA method that checks the state of the GPIOs. Otherwise : * the _STA method will always return _ON. : */ : bool enable_status; It looks the comment and name of bool need to explain a litter bit better for next person whom will define acpi power resource. Otherwise my first impression will be enable_status=0 will be _STA to off and enable_status=1 will be _STA to on. What about change to "force_on" or "always enabled" or something similar? -- To view, visit https://review.coreboot.org/c/coreboot/+/55027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91410556db002c620fd9aaa99981457808da93a5 Gerrit-Change-Number: 55027 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 01:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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