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Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs
......................................................................
soc/intel/elkhartlake: Update FSP-S storage related configs
Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC
Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
4 files changed, 87 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/10
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Change subject: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
......................................................................
Patch Set 14: Code-Review+2
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Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/elkhartlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120435):
https://review.coreboot.org/c/coreboot/+/55082/comment/8b540829_c655d834
PS9, Line 253: params->SataPortsDmVal[i] = config->SataPortsDmVal[i] ? : DEF_DMVAL;
line over 96 characters
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Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs
......................................................................
Patch Set 9:
(3 comments)
File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55082/comment/b9ace972_e42aacab
PS8, Line 84: # LPSS Serial IO (I2C/UART/GSPI) related UPDs
> I would expect this line being part of CB:54959
Ack. Unfortunately i just found the patch has been merged.
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55082/comment/705210f4_64ab6b00
PS8, Line 20: DEF_DITOVAL
> Would you mind to change it to DEF_DITOVAL_MS to clarify that this value is in ms units?
Done
https://review.coreboot.org/c/coreboot/+/55082/comment/967622f6_bcbec8e3
PS8, Line 253: params->SataPortsDmVal[i] = config->SataPortsDmVal[i] ?
: config->SataPortsDmVal[i] : DEF_DMVAL;
> Here you can shorten down the line as you are checking for a value which is assigned in the "true"-c […]
Good one! Done, thanks.
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Change subject: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
......................................................................
Patch Set 14:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54960/comment/67c135ce_c1571b82
PS13, Line 7: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings
> Please try to fit the headline on one line. MAybe something like: […]
Done
https://review.coreboot.org/c/coreboot/+/54960/comment/c8b788cb_0d1b6928
PS13, Line 9: Silicon
> silicon
Done
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Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55082
to look at the new patch set (#9).
Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs
......................................................................
soc/intel/elkhartlake: Update FSP-S storage related configs
Further add initial Silicon UPD storage settings:
- SATA
- SD card
- eMMC
Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/fsp_params.c
4 files changed, 79 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/9
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Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/54960
to look at the new patch set (#14).
Change subject: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
......................................................................
soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI
This CL also enables HECI 1 in devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/soc/intel/elkhartlake/fsp_params.c
2 files changed, 63 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/14
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55097 )
Change subject: drivers/intel/mipi_camera: Add macros to increase code readability
......................................................................
Patch Set 7: Code-Review+2
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Stefan Reinauer has removed Felix Held from this change. ( https://review.coreboot.org/c/coreboot/+/55018 )
Change subject: Documentation/community: Add Discord to forums
......................................................................
Removed reviewer Felix Held.
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55036 )
Change subject: Documentation/community: Add link to the OSF Slack
......................................................................
Documentation/community: Add link to the OSF Slack
We are also present on Slack so advertise that.
Change-Id: I7d9887e524e47e6f42a5013e9f696881ef54a631
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55036
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M Documentation/community/forums.md
1 file changed, 3 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md
index c6c913e..2ad69e1 100644
--- a/Documentation/community/forums.md
+++ b/Documentation/community/forums.md
@@ -15,7 +15,9 @@
We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
-[Discord](https://discord.gg/JqT8NM5Zbg) presence.
+[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
+[OSF Slack](https://osfw.slack.com/), which has channels on many open source
+firmware related topics.
## Fortnightly coreboot leadership meeting
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