coreboot-gerrit June 2021

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55018 ) Change subject: Documentation/community: Add Discord to forums ...................................................................... Documentation/community: Add Discord to forums Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55018 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M Documentation/community/forums.md 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md index 92eb6be..c6c913e 100644 --- a/Documentation/community/forums.md +++ b/Documentation/community/forums.md @@ -14,7 +14,8 @@ ## Real time chat We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot), -also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat). +also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a +[Discord](https://discord.gg/JqT8NM5Zbg) presence. ## Fortnightly coreboot leadership meeting -- To view, visit https://review.coreboot.org/c/coreboot/+/55018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Gerrit-Change-Number: 55018 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55018 ) Change subject: Documentation/community: Add Discord to forums ...................................................................... Patch Set 1: (1 comment) File Documentation/community/forums.md: https://review.coreboot.org/c/coreboot/+/55018/comment/b727031b_763b40f4 PS1, Line 18: [Discord](https://discord.gg/JqT8NM5Zbg) presence. > to move the discussion from the other patch here: i heard that discord bans accounts using third par […] See Stefan's assessment of the situation in the comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/55018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Gerrit-Change-Number: 55018 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 06:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Stefan Reinauer (Code Review) 01 Jun '21

01 Jun '21

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55018 ) Change subject: Documentation/community: Add Discord to forums ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I agree with Felix that some of the tools we might utilize are not ideal when it comes to how open their underlying designs are. This is true for all video chat options allowing a reasonably large number of participants, and the various iterations on what used to be just IRC back in the 90s. Personally I don't see using a tool as an endorsement for general fitness w.r.t ideology of that tool. This is a fight the coreboot project can and should fight when it comes to the tools and the software we create. When it comes to peripheral software like a chat client, I think we serve our users best if we are available everywhere, while leaving the political statements to the projects creating open source and open protocol chat / communications software. -- To view, visit https://review.coreboot.org/c/coreboot/+/55018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Gerrit-Change-Number: 55018 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 06:02:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Varshit B Pandya (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Paul Menzel, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55097 to look at the new patch set (#7). Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... drivers/intel/mipi_camera: Add macros to increase code readability This will be used to pass information to driver through ACPI in devicetree. Example https://review.coreboot.org/c/coreboot/+/52013 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" TEST=Add these macros in devicetree, build and check static.c for consistency Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd --- M src/drivers/intel/mipi_camera/chip.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/55097/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 7 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Varshit B Pandya (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Paul Menzel, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55097 to look at the new patch set (#6). Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... drivers/intel/mipi_camera: Add macros to increase code readability This will be used to pass information to driver through ACPI in devicetree. Example CL:52013 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" TEST=Add these macros in devicetree, build and check static.c for consistency Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.corp-partner.google.com> Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd --- M src/drivers/intel/mipi_camera/chip.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/55097/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: configs: Update configs for OCP Delta Lake LinuxBoot payload
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55058 ) Change subject: configs: Update configs for OCP Delta Lake LinuxBoot payload ...................................................................... configs: Update configs for OCP Delta Lake LinuxBoot payload OCP Delta Lake is developed and validated against LinuxBoot payload. Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline, CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4 is for a faster boot time. Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55058 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M configs/builder/config.ocp.deltalake 1 file changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/configs/builder/config.ocp.deltalake b/configs/builder/config.ocp.deltalake index 4a8cda1..9766b89 100644 --- a/configs/builder/config.ocp.deltalake +++ b/configs/builder/config.ocp.deltalake @@ -3,15 +3,24 @@ CONFIG_VENDOR_OCP=y CONFIG_BOARD_OCP_DELTALAKE=y +CONFIG_UART_FOR_CONSOLE=1 CONFIG_HAVE_IFD_BIN=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_LINUX_COMMAND_LINE="earlyprintk=uart8250,io,0x2f8,57600n1 console=uart8250,io,0x2f8,57600n1 intel_pstate=disable" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y CONFIG_HAVE_ME_BIN=y CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_ON_DEVICE_ROM_LOAD is not set CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y -CONFIG_CPU_UCODE_BINARIES="site-local/deltalake/mbf5065a.mcb" +CONFIG_CPU_UCODE_BINARIES="site-local/deltalake/mbf5065b.mcb" CONFIG_ADD_FSP_BINARIES=y CONFIG_FSP_T_FILE="site-local/deltalake/Server_T.fd" CONFIG_FSP_M_FILE="site-local/deltalake/Server_M.fd" CONFIG_FSP_S_FILE="site-local/deltalake/Server_S.fd" CONFIG_ME_BIN_PATH="site-local/deltalake/flashregion_2_intel_me.bin" CONFIG_IFD_BIN_PATH="site-local/deltalake/flashregion_0_flashdescriptor.bin" +CONFIG_CONSOLE_SERIAL_57600=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4=y +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/deltalake/linuxboot_uroot_ttys0" -- To view, visit https://review.coreboot.org/c/coreboot/+/55058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Gerrit-Change-Number: 55058 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 139 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index d67b217..dde0e9b 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -43,13 +43,71 @@ register "PcieClkSrcClkReq[4]" = "0x4" register "PcieClkSrcClkReq[5]" = "0x5" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C6] = PchSerialIoPci, + [PchSerialIoIndexI2C7] = PchSerialIoPci, + }" + + register "SerialIoI2cPadsTermination" = "{ + [PchSerialIoIndexI2C0] = 1, + [PchSerialIoIndexI2C1] = 1, + [PchSerialIoIndexI2C2] = 1, + [PchSerialIoIndexI2C3] = 1, + [PchSerialIoIndexI2C4] = 1, + [PchSerialIoIndexI2C5] = 1, + [PchSerialIoIndexI2C6] = 1, + [PchSerialIoIndexI2C7] = 1, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoHidden, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsEnable" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SerialIoUartDmaEnable" = "{ + [PchSerialIoIndexUART0] = 1, + [PchSerialIoIndexUART1] = 1, + [PchSerialIoIndexUART2] = 1, + }" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device device pci 08.0 off end # GNA device pci 09.0 off end # CPU Intel Trace Hub diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index ce09841..6b36792 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -167,6 +167,14 @@ uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; /* + * UARTn Default DMA/PIO Mode Enable(1)/Disable(0): + */ + uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX]; + /* + * GSPIn Default Chip Enable(1)/Disable(0): + */ + uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + /* * GSPIn Default Chip Select Mode: * 0:Hardware Mode, * 1:Software Mode @@ -178,6 +186,15 @@ * 1: High */ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; +/* + * SerialIo I2C Pads Termination Config: + * 0x0:Hardware default, + * 0x1:None, + * 0x13:1kOhm weak pull-up, + * 0x15:5kOhm weak pull-up, + * 0x19:20kOhm weak pull-up + */ + uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX]; /* * TraceHubMode config diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 3ef3b5d..5c25e95 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <string.h> /* * ME End of Post configuration @@ -45,7 +46,66 @@ static void parse_devicetree(FSP_S_CONFIG *params) { - /* TODO: Update with UPD override as FSP matures */ + const struct soc_intel_elkhartlake_config *config = config_of_soc(); + + /* LPSS controllers configuration */ + + /* I2C */ + _Static_assert(ARRAY_SIZE(params->SerialIoI2cMode) >= + ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!"); + memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, + sizeof(config->SerialIoI2cMode)); + + _Static_assert(ARRAY_SIZE(params->PchSerialIoI2cPadsTermination) >= + ARRAY_SIZE(config->SerialIoI2cPadsTermination), + "copy buffer overflow!"); + memcpy(params->PchSerialIoI2cPadsTermination, config->SerialIoI2cPadsTermination, + sizeof(config->SerialIoI2cPadsTermination)); + + params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9 + params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8 + + /* GSPI */ + _Static_assert(ARRAY_SIZE(params->SerialIoSpiMode) >= + ARRAY_SIZE(config->SerialIoGSpiMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, + sizeof(config->SerialIoGSpiMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsEnable) >= + ARRAY_SIZE(config->SerialIoGSpiCsEnable), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable, + sizeof(config->SerialIoGSpiCsEnable)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsMode) >= + ARRAY_SIZE(config->SerialIoGSpiCsMode), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode, + sizeof(config->SerialIoGSpiCsMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoSpiCsState) >= + ARRAY_SIZE(config->SerialIoGSpiCsState), "copy buffer overflow!"); + memcpy(params->SerialIoSpiCsState, config->SerialIoGSpiCsState, + sizeof(config->SerialIoGSpiCsState)); + + params->SerialIoSpiCsPolarity[2] = 0; + + /* UART */ + _Static_assert(ARRAY_SIZE(params->SerialIoUartMode) >= + ARRAY_SIZE(config->SerialIoUartMode), "copy buffer overflow!"); + memcpy(params->SerialIoUartMode, config->SerialIoUartMode, + sizeof(config->SerialIoUartMode)); + + _Static_assert(ARRAY_SIZE(params->SerialIoUartDmaEnable) >= + ARRAY_SIZE(config->SerialIoUartDmaEnable), "copy buffer overflow!"); + memcpy(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable, + sizeof(config->SerialIoUartDmaEnable)); + + params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; //GPIO native mode for GPP_T15 + params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; //GPIO native mode for GPP_T14 + params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; //GPIO native mode for GPP_T12 + params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; //GPIO native mode for GPP_T13 + + /* Provide correct UART number for FSP debug logs */ + params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; } /* UPD parameters to be initialized before SiliconInit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/car/romstage.c: Drop unused function argument
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55062 ) Change subject: cpu/intel/car/romstage.c: Drop unused function argument ...................................................................... cpu/intel/car/romstage.c: Drop unused function argument This is a leftover when migrating to C_ENV_BOOTBLOCK Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55062 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 2 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 4b4a4ab..63ddd74 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -16,7 +16,7 @@ static struct postcar_frame early_mtrrs; -static void romstage_main(unsigned long bist) +static void romstage_main(void) { int i; const int num_guards = 64; @@ -58,11 +58,6 @@ /* We do not return here. */ } -/* We don't carry BIST from bootblock in a good location to read from. - * Any error should have been reported in bootblock already. - */ -#define NO_BIST 0 - asmlinkage void car_stage_entry(void) { timestamp_add_now(TS_START_ROMSTAGE); @@ -70,5 +65,5 @@ /* Assumes the hardware was set up during the bootblock */ console_init(); - romstage_main(NO_BIST); + romstage_main(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc610cd15448632dc13d87094853d9b981e2679b Gerrit-Change-Number: 55062 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: 3rdparty/intel-sec-tools: Update to support Boot Guard
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Christopher Meis, Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55013 ) Change subject: 3rdparty/intel-sec-tools: Update to support Boot Guard ...................................................................... Patch Set 6: (2 comments) Patchset: PS4: > Had to update the commit again, because the branch in main repo was way behind master branch Does that mean it's now ready to merge? Patchset: PS6: Is this now ready for merge? The comment -- To view, visit https://review.coreboot.org/c/coreboot/+/55013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Gerrit-Change-Number: 55013 Gerrit-PatchSet: 6 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christopher Meis Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 01 Jun 2021 05:57:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christopher Meis Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Stefan Reinauer (Code Review) 01 Jun '21

01 Jun '21

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coreboot-gerrit June 2021