coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Rex-BC Chen (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Paul Menzel, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55051 to look at the new patch set (#4). Change subject: soc/mediatek: Initialize SSPM ...................................................................... soc/mediatek: Initialize SSPM Load SSPM firmware and boot up SSPM in ramstage. TEST=Load SSPM blob ok, and can see some sspm logs from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/soc.c 3 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55051/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
by Mario Scheithauer (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55089 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Gerrit-Change-Number: 55089 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 08:31:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Hung-Te Lin (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Paul Menzel, Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55051 ) Change subject: soc/mediatek: Initialize SSPM ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55051/comment/a8118fd0_d7c20e59 PS2, Line 11: TEST=none > Please do, and add how much time it adds to the boot. @Rex can you at least make sure the device still boots? File src/soc/mediatek/mt8195/Kconfig: https://review.coreboot.org/c/coreboot/+/55051/comment/97a50857_f6c2e30f PS2, Line 32: The file name of the MediaTek SSPM firmware. > Maybe add in what path the file is expected in. I'm not sure if that's needed, since most files in CBFS are in top level (root folder); this should be clear enough right? -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 08:29:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: Move the SSPM driver to common
by Hung-Te Lin (Code Review) 01 Jun '21

01 Jun '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55050 ) Change subject: soc/mediatek: Move the SSPM driver to common ...................................................................... soc/mediatek: Move the SSPM driver to common The SSPM driver can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{asurada, kukui} coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55050 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/include/soc/sspm.h R src/soc/mediatek/common/sspm.c M src/soc/mediatek/mt8183/Makefile.inc D src/soc/mediatek/mt8183/include/soc/sspm.h M src/soc/mediatek/mt8192/Makefile.inc D src/soc/mediatek/mt8192/include/soc/sspm.h D src/soc/mediatek/mt8192/sspm.c 7 files changed, 17 insertions(+), 56 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/sspm.h b/src/soc/mediatek/common/include/soc/sspm.h new file mode 100644 index 0000000..ff405ce --- /dev/null +++ b/src/soc/mediatek/common/include/soc/sspm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_SSPM_H +#define SOC_MEDIATEK_COMMON_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct sspm_regs { + u32 sw_rstn; +}; +static struct sspm_regs *const sspm_reg = (void *)SSPM_CFG_BASE; +void sspm_init(void); +#endif /* SOC_MEDIATEK_COMMON_SSPM_H */ diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/common/sspm.c similarity index 92% rename from src/soc/mediatek/mt8183/sspm.c rename to src/soc/mediatek/common/sspm.c index e0ac84a..0a4d5b0 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/common/sspm.c @@ -7,7 +7,7 @@ static void reset_sspm(struct mtk_mcu *mcu) { - write32(&mt8183_sspm->sw_rstn, 0x1); + write32(&sspm_reg->sw_rstn, 0x1); } static struct mtk_mcu sspm = { diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index e0ec810..2cf8133 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -58,7 +58,7 @@ ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += spm.c -ramstage-y += sspm.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h deleted file mode 100644 index 23160a8..0000000 --- a/src/soc/mediatek/mt8183/include/soc/sspm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_MT8183_SSPM_H -#define SOC_MEDIATEK_MT8183_SSPM_H - -#include <soc/addressmap.h> -#include <types.h> - -struct mt8183_sspm_regs { - u32 sw_rstn; -}; -static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_CFG_BASE; -void sspm_init(void); -#endif /* SOC_MEDIATEK_MT8183_SSPM_H */ diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index bdff835..0943e7c 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -61,7 +61,7 @@ ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += spm.c -ramstage-y += sspm.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h deleted file mode 100644 index 5749fa4..0000000 --- a/src/soc/mediatek/mt8192/include/soc/sspm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_MT8192_SSPM_H -#define SOC_MEDIATEK_MT8192_SSPM_H - -#include <soc/addressmap.h> -#include <types.h> - -struct mt8192_sspm_regs { - u32 sw_rstn; -}; -static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE; -void sspm_init(void); -#endif /* SOC_MEDIATEK_MT8192_SSPM_H */ diff --git a/src/soc/mediatek/mt8192/sspm.c b/src/soc/mediatek/mt8192/sspm.c deleted file mode 100644 index cce08c2..0000000 --- a/src/soc/mediatek/mt8192/sspm.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <soc/mcu_common.h> -#include <soc/sspm.h> -#include <soc/symbols.h> - -static void reset_sspm(struct mtk_mcu *mcu) -{ - write32(&mt8192_sspm->sw_rstn, 0x1); -} - -static struct mtk_mcu sspm = { - .firmware_name = CONFIG_SSPM_FIRMWARE, - .run_address = (void *)SSPM_SRAM_BASE, - .reset = reset_sspm, -}; - -void sspm_init(void) -{ - sspm.load_buffer = _dram_dma; - sspm.buffer_size = REGION_SIZE(dram_dma); - - mtk_init_mcu(&sspm); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/55050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Gerrit-Change-Number: 55050 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/siemens/mc_apl2: Disable unused I2C controllers
by Mario Scheithauer (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55090 ) Change subject: mb/siemens/mc_apl2: Disable unused I2C controllers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Gerrit-Change-Number: 55090 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 08:28:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
by Anand Mistry (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Martin Roth, Paul Menzel, Werner Zeh. Anand Mistry has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55001 ) Change subject: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/stoneyridge/acpi.c: https://review.coreboot.org/c/coreboot/+/55001/comment/43bc91c0_925f5e10 PS3, Line 87: fadt->century = 0x32; > Hi Could you please have a look at CB:55012 and tell me what you think? That looks good to me, but I can only talk about stoneyridge/picasso. I don't normally work on coreboot, so I don't have much of an opinion otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/55001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1 Gerrit-Change-Number: 55001 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Mistry <amistry(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 07:56:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
by Johnny Lin (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Rocky Phagura, Arthur Heymans, Morgan Jang, Patrick Rudolph. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55098 ) Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3 Gerrit-Change-Number: 55098 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 07:54:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Werner Zeh (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55082 ) Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55082/comment/ce9b82a2_f7b7291c PS12, Line 253: params->SataPortsDmVal[i] = config->SataPortsDmVal[i] ? : : DEF_DMVAL; : params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i] ? : : DEF_DITOVAL_MS; I would ratgher break the line after the "=", e.i.: params->SataPortsDmVal[i] = config->SataPortsDmVal[i] ? : DEF_DMVAL; -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 07:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#12). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 80 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#11). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 80 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 11 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021