coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna). Hello build bot (Jenkins), Nico Huber, Paul Menzel, Arthur Heymans, Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55169 to look at the new patch set (#2). Change subject: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports ...................................................................... mb/lenovo/t410: Enable WLAN and WUSB PCIe ports These PCH PCIe ports are used and should be enabled. Resolves: https://ticket.coreboot.org/issues/311 Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/55169/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled
by Subrata Banik (Code Review) 03 Jun '21

03 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55170 ) Change subject: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled ...................................................................... mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled TEST=Make sure FSP is not programming I2C4. Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55170/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index ddb1ece..b41a76d 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -68,7 +68,7 @@ [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/55170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Gerrit-Change-Number: 55170 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (2 comments) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/02cf4c4c_eae27e8d PS1, Line 206: PXSX > @Tim: Once the change lands, you will have to update Intel platforms to expose the _DSD property und […] The change shouldn't affect functionality. It would just be a cleanup if you wanted to rename the PSXS acpi node. https://review.coreboot.org/c/coreboot/+/54966/comment/616c8ced_e996e49e PS1, Line 210: pci_dev_read_resources > > So is the driver good as is then? […] I'll do that and push up a change. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:44:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Enable WWAN and WUSB PCIe ports
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WWAN and WUSB PCIe ports ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Change looks fine but from schematics I think comment should be swapped around - port #1 being WWAN […] Looks like the comments show the mapping on preproduction boards [old], and production boards use a different mapping [new]. [old]: https://i.imgur.com/eb0CqN9.png [new]: https://i.imgur.com/whvBKmr.png -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (2 comments) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/4cf95295_d4ba8e75 PS1, Line 206: PXSX > Looks like the upstream patch has been tested on the original hardware. […] @Tim: Once the change lands, you will have to update Intel platforms to expose the _DSD property under the correct ACPI device. https://review.coreboot.org/c/coreboot/+/54966/comment/bd8a4571_0f9ac526 PS1, Line 210: pci_dev_read_resources > So is the driver good as is then? Yes, it looks good to me. > Should I just call pci_rom_ssdt from the rtd3 ssdt method? You will need both `pci_rom_write_acpi_tables` and `pci_rom_ssdt`. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:37:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Raul Rangel (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Paul Menzel, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54966/comment/2758718b_65e9881b PS1, Line 9: I decided : to copy and modify it because the Intel driver has a lot of Intel : specific code. > Thanks Raul! Done File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/b277f36f_a2f8b515 PS1, Line 109: Name (_PR2, Package (0x01) // _PR2: Power Resources for D2 : * { : * RTD3 : * }) > Please also mention this difference in the commit message. Removed _PR2, so no longer relevant. https://review.coreboot.org/c/coreboot/+/54966/comment/448e7dcd_55b157f3 PS1, Line 206: PXSX > Thanks Raul! Looks like the upstream patch has been tested on the original hardware. I'll get that pulled into our tree. https://review.coreboot.org/c/coreboot/+/54966/comment/e655a741_0d83a252 PS1, Line 210: pci_dev_read_resources No worries, glad we hashed it out. At least we know why we are doing it this way now :) So is the driver good as is then? > Probably make a note that the driver does not handle any downstream graphics devices? Should I just call pci_rom_ssdt from the rtd3 ssdt method? https://review.coreboot.org/c/coreboot/+/54966/comment/8bb9366d_2c8c5ce4 PS1, Line 221: drivers_nvme_generic_config > Is it soc_amd_common_block_rtd3_config? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Enable WWAN and WUSB PCIe ports
by Swift Geek (Sebastian Grzywna) (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Swift Geek (Sebastian Grzywna) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WWAN and WUSB PCIe ports ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Change looks fine but from schematics I think comment should be swapped around - port #1 being WWAN and port #2 WLAN. WUSB/ExpressCard/Card reader appear to be correct Checked against documentation of both iGPU and dGPU variants of nozomi-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:27:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/2f165803_77e54154 PS1, Line 210: pci_dev_read_resources > I guess if you have a "naked" nvme device like that (no chip) and you need ACPI entries... […] Hehe. Looks like we have come a full circle here :P. Sorry about the back n forth Raul. What you had initially proposed with a separate chip driver for rtd3 does seem like the better approach. We can ignore the case of bridges for now and just focus on the non-bridge devices downstream by setting PCI ops same as default_pci_ops. Probably make a note that the driver does not handle any downstream graphics devices? -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:19:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/81a69901_848d1d2b PS1, Line 210: pci_dev_read_resources > No, the root port is handled by the AMD PCIe GPP driver. I mean the actual NVMe device node. […] I guess if you have a "naked" nvme device like that (no chip) and you need ACPI entries... then you'll have to add a chip ;) IMHO the right way is to make sure it has a chip of some kind (one that generates the device in the SSDT); if that is an assumption then maybe the documentation needs to get updated too. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:12:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2021