June 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 11: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120637): https://review.coreboot.org/c/coreboot/+/55128/comment/4ddaf923_116003a8 PS11, Line 115: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:15:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: move MIPI camera setting into overridetree
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55134 ) Change subject: mb/google/brya: move MIPI camera setting into overridetree ...................................................................... mb/google/brya: move MIPI camera setting into overridetree In order to support no MIPI camera variant, move related configuration into variant folder. BUG=b:188272162 BRANCH=none TEST=build no MIPI camera variant without error Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55134 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 83 insertions(+), 86 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index ddb1ece..36635fb 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -129,19 +129,6 @@ device domain 0 on device ref igpu on end device ref dtt on end - device ref ipu on - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used - register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" - register "cio2_prt[0]" = "2" - device generic 0 on end - end - end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end device ref tbt_pcie_rp2 on end @@ -156,78 +143,6 @@ device generic 0 on end end end - - device ref i2c0 on - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI8856"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 8856 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - - register "ssdb.lanes_used" = "4" - register "ssdb.link_used" = "0" - register "ssdb.vcm_type" = "0x0C" - register "vcm_name" = ""VCM0"" - register "num_freq_entries" = "2" - register "link_freq[0]" = "360 * MHz" # 360 MHz - register "link_freq[1]" = "180 * MHz" # 180 MHz - register "remote_name" = ""IPU0"" - - register "has_power_resource" = "1" - #Controls - register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" - register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" - - register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 - register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 - register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset - - #_ON - register "on_seq.ops_cnt" = "5" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" - - #_OFF - register "off_seq.ops_cnt" = "4" - register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - - device i2c 10 on end - end - chip drivers/intel/mipi_camera - register "acpi_uid" = "2" - register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW9768 VCM"" - register "device_type" = "INTEL_ACPI_CAMERA_VCM" - - register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" - register "vcm_compat" = ""dongwoon,dw9768"" - - device i2c 0C on end - end - chip drivers/intel/mipi_camera - register "acpi_uid" = "1" - register "acpi_name" = ""NVM0"" - register "chip_name" = ""AT24 EEPROM"" - register "device_type" = "INTEL_ACPI_CAMERA_NVM" - - register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" - register "nvm_compat" = ""atmel,24c1024"" - - register "nvm_size" = "0x2800" - register "nvm_pagesize" = "0x01" - register "nvm_readonly" = "0x01" - register "nvm_width" = "0x0E" - - device i2c 58 on end - end - end #I2C0 device ref i2c3 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 452e1d8..78fc472 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -116,6 +116,19 @@ device generic 0 on end end end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" @@ -146,7 +159,76 @@ register "property_list[0].integer" = "1" device i2c 1a on end end - end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI8856"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 8856 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "2" + register "link_freq[0]" = "360 * MHz" # 360 MHz + register "link_freq[1]" = "180 * MHz" # 180 MHz + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 10 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9768 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9768"" + + device i2c 0C on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""AT24 EEPROM"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C0.CAM0.PRIC"" + register "nvm_compat" = ""atmel,24c1024"" + + register "nvm_size" = "0x2800" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + device i2c 58 on end + end + end #I2C0 device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" -- To view, visit https://review.coreboot.org/c/coreboot/+/55134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Gerrit-Change-Number: 55134 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Sean Rhodes, Andy Pont. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 13: Code-Review+2 (2 comments) File src/ec/starlabs/it8987/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/52797/comment/7b5316cd_218b24db PS12, Line 373: : // Method(_Q45) // SMM Mode - Not used in coreboot : // { : // SMB2 = 0xC1 : // } > Plan to use it in the future - hence it being left Ack File src/ec/starlabs/it8987/acpi/hid.asl: PS12: > Reminder of the original source I guess. It's been happy for months now so it can go. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:10:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update ACPI device ID of IOM
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Patrick Rudolph, Azhar Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54859 ) Change subject: soc/intel/alderlake: Update ACPI device ID of IOM ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54859/comment/4f26cebf_02ede2a0 PS1, Line 13: Let's add: `Cq-Depend: chromium:2936144` for the kernel patch, and then I'll try to land them at the same time. -- To view, visit https://review.coreboot.org/c/coreboot/+/54859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdfcd0c1534e8204719e59e718688cd42e846e84 Gerrit-Change-Number: 54859 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Azhar Shaikh <azhar.shaikh(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Azhar Shaikh <azhar.shaikh(a)intel.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Matt DeVillier (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Martin Roth, Benjamin Doron. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Maybe add that it substantially increases the final payload size? As I recall, it's some 300 KB larg […] comparing a release build w/ and w/o this option selected, it's ~215k larger (755k vs 971k). I'll add a note :) -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:07:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 10: (1 comment) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120635): https://review.coreboot.org/c/coreboot/+/55128/comment/ef0e6844_4bb729f4 PS10, Line 115: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:06:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/mainboard: Add Star Labs labtop series
by Tim Wawrzynczak (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Sean Rhodes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55128 ) Change subject: src/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 9: Code-Review+1 (7 comments) Patchset: PS9: Few more nits, mostly LGTM File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/55128/comment/75c7b640_a8a12305 PS6, Line 11: ### Purism : : [Purism](https://www.puri.sm) sells laptops with a focus on user privacy and : security; part of that effort is to minimize the amount of proprietary and/or : binary code. Their laptops ship with a blob-free OS and coreboot firmware : with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. > I was bundling all the documentation into one, seemed to miss the relevant 'Documentation/mainboard/ […] Ack File Documentation/mainboard/starlabs/labtop.md: https://review.coreboot.org/c/coreboot/+/55128/comment/5036d716_739f5921 PS9, Line 120: higher than **1.5.6** will work. : ![fwupd version](https://cdn.shopify.com/s/files/1/2059/5897/files/fwupdV.png?v=161… : On Ubuntu 20.04, Ubuntu 20.10, Linux Mint 20.1 and elementaryOS 6, fwupd 1.5.6 can be installed from our PPA with the below terminal commands: : sounds like you mean 1.5.6 and greater will work? File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/55128/comment/834a527b_5709426f PS6, Line 26: # select HAVE_IFD_BIN : # select HAVE_ME_BIN > ME and Descriptor aren't in the blobs repository, which causes the build to fail. […] Ack File src/mainboard/starlabs/labtop/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/55128/comment/31540f01_8ace18fe PS9, Line 55: Sorry I mean there's a tab between #define and EC_GPE_SWI, should be a space File src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex: PS6: > No, just as the hex files already existed in the tree. […] This is fine; the spd_tools are really neat, though, if you have access to the datasheet for the memory part; it can generate an SPD file for some Intel & AMD chipsets automatically. I think it would need some porting work for CML or KBL, though. File src/mainboard/starlabs/labtop/variants/cml/romstage.c: https://review.coreboot.org/c/coreboot/+/55128/comment/96dc6be9_e799eb78 PS6, Line 41: (gpio_get(GPP_H6) < 2) | (gpio_get(GPP_E23) < 1) | gpio_get(GPP_E22); > suggestion: use `gpio_base2_value` function, e.g.: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Gerrit-Change-Number: 55128 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Thu, 03 Jun 2021 15:03:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Override I2C3 pad configuration
by Raul Rangel (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Furquan Shaikh, Martin Roth, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55149 ) Change subject: mb/google/guybrush: Override I2C3 pad configuration ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/i2c.c: https://review.coreboot.org/c/coreboot/+/55149/comment/36d6fc17_1cc42a1e PS1, Line 8: mainboard_i2c_override > What do you think about moving this to a devicetree config? That will eliminate the need for the cal […] +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Gerrit-Change-Number: 55149 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 14:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Enable WWAN and WUSB PCIe ports
by Angel Pons (Code Review) June 3, 2021

June 3, 2021

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WWAN and WUSB PCIe ports ...................................................................... mb/lenovo/t410: Enable WWAN and WUSB PCIe ports These PCH PCIe ports are used and should be enabled. Resolves: https://ticket.coreboot.org/issues/311 Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/55169/1 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 5f167df..a0c9a64 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -72,8 +72,8 @@ end device pci 1c.0 on end # PCIe Port #1 (wlan) - device pci 1c.1 off end # PCIe Port #2 (wwan) - device pci 1c.2 off end # PCIe Port #3 (wusb) + device pci 1c.1 on end # PCIe Port #2 (wwan) + device pci 1c.2 on end # PCIe Port #3 (wusb) device pci 1c.3 on end # PCIe Port #4 (ExpressCard) device pci 1c.4 on subsystemid 0x17aa 0x2133 -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]amdfwtool: Add a script to replace AMD firmware
by Bao Zheng (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55160 ) Change subject: [WIP]amdfwtool: Add a script to replace AMD firmware ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55160/comment/294beb99_22bf76dd PS2, Line 7: [WIP]amdfwtool: Add a script to replace AMD firmware b:183447172 -- To view, visit https://review.coreboot.org/c/coreboot/+/55160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Gerrit-Change-Number: 55160 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 03 Jun 2021 14:26:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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