coreboot-gerrit June 2021

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Change in coreboot[master]: Ada: Enable the newest Ada standard + extensions supported by gnat
by Patrick Georgi (Code Review) 03 Jun '21

03 Jun '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55168 ) Change subject: Ada: Enable the newest Ada standard + extensions supported by gnat ...................................................................... Ada: Enable the newest Ada standard + extensions supported by gnat We're a bit in a bind here: The only way to declare an array containing atomic or volatile members is to mark the member type atomic or volatile as well. The only way to mark a member type atomic or volatile seems to be to use Ada202x. Change-Id: If2f627bdf7f29ffdd4433b4ca608b2291ebe1551 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/55168/1 diff --git a/Makefile.inc b/Makefile.inc index eb505e5..fce53fa 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -435,7 +435,7 @@ endif endif -ADAFLAGS_common += -gnatp +ADAFLAGS_common += -gnatp -gnatX ADAFLAGS_common += -Wuninitialized -Wall -Werror ADAFLAGS_common += -pipe -g -nostdinc ADAFLAGS_common += -Wstrict-aliasing -Wshadow -- To view, visit https://review.coreboot.org/c/coreboot/+/55168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f627bdf7f29ffdd4433b4ca608b2291ebe1551 Gerrit-Change-Number: 55168 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in libhwbase[master]: Make gcc11 compatible
by Patrick Georgi (Code Review) 03 Jun '21

03 Jun '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/libhwbase/+/55167 ) Change subject: Make gcc11 compatible ...................................................................... Make gcc11 compatible It's much more picky when dealing with arrays containing volatile or atomic members. Meanwhile System.Address_To_Access_Conversions doesn't seem to be able to return an element with atomic/volatile aspect, so everything fell apart. Entire untested except that it builds (for me) Change-Id: Ieb50c4dd8ba96248c3051a7282f9e5cdbb270344 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M ada/dynamic_mmio/hw-mmio_range.adb M common/hw-mmio_range.ads M common/hw-pci-dev.ads M common/hw-pci-mmconf.adb M common/hw-pci-mmconf.ads 5 files changed, 30 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/67/55167/1 diff --git a/ada/dynamic_mmio/hw-mmio_range.adb b/ada/dynamic_mmio/hw-mmio_range.adb index 86c8d1b..60cbbd5 100644 --- a/ada/dynamic_mmio/hw-mmio_range.adb +++ b/ada/dynamic_mmio/hw-mmio_range.adb @@ -14,14 +14,12 @@ with HW.Debug; with GNAT.Source_Info; -with System.Storage_Elements; -with System.Address_To_Access_Conversions; package body HW.MMIO_Range with Refined_State => - (State => null, -- the contents accessed, Range_A points to it - Base_Address => Range_A) -- the address, stored in Range_A + (State => null, -- the contents accessed, Base points to it + Base_Address => (Base, Range_A)) -- the address, stored in Base is pragma Warnings (Off, "implicit dereference", Reason => "This is what this package is about."); @@ -29,12 +27,6 @@ Debug_Reads : constant Boolean := False; Debug_Writes : constant Boolean := False; - type Range_Access is access all Array_T; - package Conv_Range is new System.Address_To_Access_Conversions (Array_T); - - Range_A : Range_Access := - Range_Access (Conv_Range.To_Pointer (System'To_Address (Base_Addr))); - procedure Read (Value : out Element_T; Index : in Index_T) is use type Word32; @@ -45,9 +37,8 @@ pragma Debug (Debug_Reads, Debug.Put_Word32 (Word32 (Value))); pragma Debug (Debug_Reads, Debug.Put (" <- ")); pragma Debug (Debug_Reads, Debug.Put_Word32 - (Word32 (System.Storage_Elements.To_Integer - (Conv_Range.To_Address (Conv_Range.Object_Pointer (Range_A)))) + - Word32 (Index) * (Element_T'Size / 8))); + (Word32 (System.Storage_Elements.To_Integer (Base)) + + Word32 (Index) * (Element_T'Size / 8))); pragma Debug (Debug_Reads, Debug.New_Line); end Read; @@ -60,17 +51,17 @@ pragma Debug (Debug_Writes, Debug.Put_Word32 (Word32 (Value))); pragma Debug (Debug_Writes, Debug.Put (" -> ")); pragma Debug (Debug_Writes, Debug.Put_Word32 - (Word32 (System.Storage_Elements.To_Integer - (Conv_Range.To_Address (Conv_Range.Object_Pointer (Range_A)))) + - Word32 (Index) * (Element_T'Size / 8))); + (Word32 (System.Storage_Elements.To_Integer (Base)) + + Word32 (Index) * (Element_T'Size / 8))); pragma Debug (Debug_Writes, Debug.New_Line); Range_A (Index) := Value; end Write; - procedure Set_Base_Address (Base : Word64) is + procedure Set_Base_Address (New_Base : Word64) is + Address : System.Storage_Elements.Integer_Address; begin - Range_A := Range_Access - (Conv_Range.To_Pointer (System'To_Address (Base))); + Address := System.Storage_Elements.Integer_Address (New_Base); + Base := System.Storage_Elements.To_Address(Address); end Set_Base_Address; end HW.MMIO_Range; diff --git a/common/hw-mmio_range.ads b/common/hw-mmio_range.ads index 8495f73..86ddcd6 100644 --- a/common/hw-mmio_range.ads +++ b/common/hw-mmio_range.ads @@ -13,17 +13,17 @@ -- with System; +with System.Storage_Elements; generic Base_Addr : Word64; type Element_T is mod <>; type Index_T is range <>; - type Array_T is array (Index_T) of Element_T; package HW.MMIO_Range with Abstract_State => ((State with External), - Base_Address), + (Base_Address with External)), Initializes => Base_Address is @@ -31,6 +31,18 @@ procedure Write (Index : in Index_T; Value : in Element_T); - procedure Set_Base_Address (Base : Word64); + procedure Set_Base_Address (New_Base : Word64); + +private + + Base : System.Address := System.Storage_Elements.To_Address + (System.Storage_Elements.Integer_Address (Base_Addr)) + with Part_Of => Base_Address; + + type Volatile_Element_T is new Element_T with Volatile; + type Array_T is array (Index_T) of Element_T with Volatile_Components; + + Range_A : Array_T with Part_Of => Base_Address; + for Range_A'Address use Base; end HW.MMIO_Range; diff --git a/common/hw-pci-dev.ads b/common/hw-pci-dev.ads index 5b20aa1..6bfef74 100644 --- a/common/hw-pci-dev.ads +++ b/common/hw-pci-dev.ads @@ -16,7 +16,7 @@ Dev : PCI.Address := (0, 0, 0); package HW.PCI.Dev with - Abstract_State => (Address_State, (PCI_State with External)), + Abstract_State => ((Address_State with External), (PCI_State with External)), Initializes => Address_State is diff --git a/common/hw-pci-mmconf.adb b/common/hw-pci-mmconf.adb index 180f2d7..493780d 100644 --- a/common/hw-pci-mmconf.adb +++ b/common/hw-pci-mmconf.adb @@ -29,16 +29,12 @@ type Index16 is new Index range 0 .. Index'Last / 2; type Index32 is new Index range 0 .. Index'Last / 4; - type Array8 is array (Index) of Byte with Atomic_Components; - type Array16 is array (Index16) of Word16 with Atomic_Components; - type Array32 is array (Index32) of Word32 with Atomic_Components; - package MM8 is new HW.MMIO_Range - (Default_Base_Address, Word8, Index, Array8); + (Default_Base_Address, Word8, Index); package MM16 is new HW.MMIO_Range - (Default_Base_Address, Word16, Index16, Array16); + (Default_Base_Address, Word16, Index16); package MM32 is new HW.MMIO_Range - (Default_Base_Address, Word32, Index32, Array32); + (Default_Base_Address, Word32, Index32); procedure Read8 (Value : out Word8; Offset : Index) renames MM8.Read; diff --git a/common/hw-pci-mmconf.ads b/common/hw-pci-mmconf.ads index 597ebfa..22e2e2e 100644 --- a/common/hw-pci-mmconf.ads +++ b/common/hw-pci-mmconf.ads @@ -21,7 +21,7 @@ Dev : Address := (0, 0, 0); package HW.PCI.MMConf with - Abstract_State => (Address_State, (PCI_State with External)), + Abstract_State => ((Address_State with External), (PCI_State with External)), Initializes => Address_State is -- To view, visit https://review.coreboot.org/c/libhwbase/+/55167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Change-Id: Ieb50c4dd8ba96248c3051a7282f9e5cdbb270344 Gerrit-Change-Number: 55167 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Hung-Te Lin (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/b5a4c2fc_bedc046f PS1, Line 9: Fix GPIO pu/pd offset. Do you have a reference for these offsets so we can know it's now correct? Maybe which chapter in the data sheet / application doc ? -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 13:46:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in libgfxinit[master]: Adapt to gcc11 compatible libhwbase API
by Patrick Georgi (Code Review) 03 Jun '21

03 Jun '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/55166 ) Change subject: Adapt to gcc11 compatible libhwbase API ...................................................................... Adapt to gcc11 compatible libhwbase API Change-Id: I0054920b27d4c6ee75f2caa9a6c9b5005a694045 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M common/hw-gfx-framebuffer_filler.adb M common/hw-gfx-framebuffer_filler.ads M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads 5 files changed, 7 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/66/55166/1 diff --git a/common/hw-gfx-framebuffer_filler.adb b/common/hw-gfx-framebuffer_filler.adb index 29c7da6..8df556d 100644 --- a/common/hw-gfx-framebuffer_filler.adb +++ b/common/hw-gfx-framebuffer_filler.adb @@ -23,8 +23,7 @@ type FB_Index is new Natural range 0 .. Natural (Width_Type'Last * Height_Type'Last) - 1; - type FB_Range is array (FB_Index) of Word32 with Pack; - package FB is new MMIO_Range (0, Word32, FB_Index, FB_Range); + package FB is new MMIO_Range (0, Word32, FB_Index); procedure Fill (Linear_FB : Word64; Framebuffer : Framebuffer_Type) is diff --git a/common/hw-gfx-framebuffer_filler.ads b/common/hw-gfx-framebuffer_filler.ads index 7ad3b79..4ad685e 100644 --- a/common/hw-gfx-framebuffer_filler.ads +++ b/common/hw-gfx-framebuffer_filler.ads @@ -20,7 +20,7 @@ package HW.GFX.Framebuffer_Filler with - Abstract_State => ((State with External), Base_Address), + Abstract_State => ((State with External), (Base_Address with External)), Initializes => Base_Address is diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 3f0d7ae..b92102c 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -33,39 +33,24 @@ type Registers_Range is new Natural range 0 .. 16#0020_0000# / Register_Width - 1; - type Registers_Type is array (Registers_Range) of Word32 - with - Atomic_Components, - Size => 16#20_0000# * 8; package Regs is new MMIO_Range (Base_Addr => Config.Default_MMIO_Base, Element_T => Word32, - Index_T => Registers_Range, - Array_T => Registers_Type); + Index_T => Registers_Range); ---------------------------------------------------------------------------- type GTT_PTE_32 is mod 2 ** 32; - type GTT_Registers_32 is array (GTT_Range) of GTT_PTE_32 - with - Volatile_Components, - Size => MMIO_GTT_32_Size * 8; package GTT_32 is new MMIO_Range (Base_Addr => Config.Default_MMIO_Base + MMIO_GTT_32_Offset, Element_T => GTT_PTE_32, - Index_T => GTT_Range, - Array_T => GTT_Registers_32); + Index_T => GTT_Range); type GTT_PTE_64 is mod 2 ** 64; - type GTT_Registers_64 is array (GTT_Range) of GTT_PTE_64 - with - Volatile_Components, - Size => MMIO_GTT_64_Size * 8; package GTT_64 is new MMIO_Range (Base_Addr => Config.Default_MMIO_Base + MMIO_GTT_64_Offset, Element_T => GTT_PTE_64, - Index_T => GTT_Range, - Array_T => GTT_Registers_64); + Index_T => GTT_Range); GTT_PTE_Valid : constant := 1; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 3318ab1..1a0c644 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -19,7 +19,7 @@ private package HW.GFX.GMA.Registers with Abstract_State => - ((Address_State with Part_Of => GMA.State), + ((Address_State with External, Part_Of => GMA.State), (Register_State with External, Part_Of => GMA.Device_State), (GTT_State with External, Part_Of => GMA.Device_State)), Initializes => Address_State diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index afd1512..d946b99 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -22,7 +22,7 @@ package HW.GFX.GMA with Abstract_State => - (State, + ((State with External), Init_State, (Device_State with External)), Initializes => Init_State -- To view, visit https://review.coreboot.org/c/libgfxinit/+/55166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I0054920b27d4c6ee75f2caa9a6c9b5005a694045 Gerrit-Change-Number: 55166 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/blipper: Update DPTF parameters
by Sumeet R Pawnikar (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Henry Sun, Tao Xia, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54715 ) Change subject: mb/google/dedede/var/blipper: Update DPTF parameters ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379c0ea79a7c27bdd81ed41a54135f7284fb6412 Gerrit-Change-Number: 54715 Gerrit-PatchSet: 2 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 12:24:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Add SKU specific power limits support
by Sumeet R Pawnikar (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Rajasekhar Venkatanagapavan, Patrick Rudolph, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54676 ) Change subject: soc/intel/adl: Add SKU specific power limits support ...................................................................... Patch Set 8: (1 comment) File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54676/comment/2efc76f2_61561c50 PS8, Line 137: register "power_limits_config" = "{ : .tdp_pl1_override = 45, : .tdp_pl2_override = 56, : }" : > adlrvp still needs to override these, or else this patch will change them to 45 and 115 These values were not appropriate earlier and not required anymore. All updated values are part of chipset.cb file as per doc mentioned in commit message. I have tested this patch and it works fine on adlrvp and brya boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/54676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Gerrit-Change-Number: 54676 Gerrit-PatchSet: 8 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rajasekhar Venkatanagapavan <rajasekhar.venkatanagapavan(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rajasekhar Venkatanagapavan <rajasekhar.venkatanagapavan(a)intel.corp-partner.google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 12:18:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/elemi: Include SPD for MT40A512M16TB-062E:R
by Chen Wisley (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak, Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55165 to review the following change. Change subject: mb/google/volteer/variants/elemi: Include SPD for MT40A512M16TB-062E:R ...................................................................... mb/google/volteer/variants/elemi: Include SPD for MT40A512M16TB-062E:R Add SPD support to elemi for MT40A512M16TB-062E:R BUG=b:190020997 TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-bootimage Change-Id: I548ea2ec01dd0a43442a691cf870c2bc1b58bc74 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc M src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/55165/1 diff --git a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc index 3b8bf21..a70a7d9 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc @@ -4,5 +4,5 @@ SPD_SOURCES = SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE -SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE, MT40A512M16TB-062E:R SPD_SOURCES += ddr4-spd-9.hex # ID = 3(0b0011) Parts = H5ANAG6NCJR-XNC, K4AAG165WB-BCWE diff --git a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt index 57e44a9..2e12aff 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt @@ -7,3 +7,4 @@ K4A8G165WC-BCWE 2 (0010) H5ANAG6NCJR-XNC 3 (0011) K4AAG165WB-BCWE 3 (0011) +MT40A512M16TB-062E:R 2 (0010) diff --git a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt index 5445b61..87f6d30 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt @@ -6,3 +6,4 @@ K4A8G165WC-BCWE H5ANAG6NCJR-XNC K4AAG165WB-BCWE +MT40A512M16TB-062E:R -- To view, visit https://review.coreboot.org/c/coreboot/+/55165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I548ea2ec01dd0a43442a691cf870c2bc1b58bc74 Gerrit-Change-Number: 55165 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util: Add DDR4 generic SPD for MT40A512M16TB-062E:R
by Chen Wisley (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55164 to review the following change. Change subject: util: Add DDR4 generic SPD for MT40A512M16TB-062E:R ...................................................................... util: Add DDR4 generic SPD for MT40A512M16TB-062E:R Add SPD support for DDR4 memory part BUG=190020997 TEST=none Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55164/1 diff --git a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt index 96fb261..4fdf0dd 100644 --- a/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt @@ -15,3 +15,5 @@ H5ANAG6NDMR-XNC,ddr4-spd-2.hex H5ANAG6NCJR-XNC,ddr4-spd-9.hex K4AAG165WB-BCWE,ddr4-spd-9.hex +MT40A1G16RC-062E:B,ddr4-spd-9.hex +MT40A512M16TB-062E:R,ddr4-spd-1.hex diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 03c6630..18e6052 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -227,6 +227,17 @@ "packageBusWidth": 16, "ranksPerPackage": 1 } + }, + { + "name": "MT40A512M16TB-062E:R", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 8, + "diesPerPackage": 1, + "packageBusWidth": 16, + "ranksPerPackage": 1 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/55164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Gerrit-Change-Number: 55164 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Arthur Heymans (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Sean Rhodes, Andy Pont, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 25: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/52800/comment/41e36a86_a13da649 PS20, Line 847: print_me_fw_version > If the ME is enabled, and we want to disable it, we don't want to reset heci. It wont cover that. You probably don't want to get the firmware revision after that either which is what this function does. What I propose is to add an .enable to the device_operations. This will be run before resources are probed and allocated and also before printing the version is run. This should cover your usecase. -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 25 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 11:10:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... soc/mediatek/mt8195: fix GPIO register offset Fix GPIO pu/pd offset. Signed-off-by: Zhiqiang Ma <zhiqiang.ma(a)mediatek.com> Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 --- M src/soc/mediatek/mt8195/include/soc/gpio.h 1 file changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55163/1 diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 0739f63..e5c1ff1 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -56,40 +56,40 @@ PIN(5, GPIO_05, 1, 5, 0x23, 0x60, TP_GPIO5_AO, MSDC2_DAT1, SPDIF_IN0, URXD3, SCL2, RES6, USB_DRVVBUS_2P), - PIN(6, GPIO_06, 0, 6, 0x23, 0x70, + PIN(6, GPIO_06, 0, 0, 0x23, 0x70, TP_GPIO6_AO, DP_TX_HPD, I2SO1_D4, UTXD4, CMVREF3, RES6, DMIC3_CLK), - PIN(7, GPIO_07, 0, 7, 0x23, 0x70, + PIN(7, GPIO_07, 0, 1, 0x23, 0x70, TP_GPIO7_AO, EDP_TX_HPD, I2SO1_D5, URXD4, CMVREF4, RES6, DMIC3_DAT), - PIN(8, SDA0, 0, 13, 0x23, 0x70, + PIN(8, SDA0, 0, 7, 0x23, 0x70, SDA0, PWM_0, RES3, SPDIF_OUT, RES5, LVTS_FOUT, DBG_MON_A0), - PIN(9, SCL0, 0, 8, 0x23, 0x70, + PIN(9, SCL0, 0, 2, 0x23, 0x70, SCL0, PWM_1, RES3, IR_IN, RES5, LVTS_SDO, DBG_MON_A1), - PIN(10, SDA1, 0, 14, 0x23, 0x70, + PIN(10, SDA1, 0, 8, 0x23, 0x70, SDA1, PWM_2, ADSP_URXD0, SPDIF_IN1, RES5, LVTS_SCF, DBG_MON_A2), - PIN(11, SCL1, 0, 9, 0x23, 0x70, + PIN(11, SCL1, 0, 3, 0x23, 0x70, SCL1, PWM_3, ADSP_UTXD0, SPDIF_IN0, RES5, LVTS_SCK, DBG_MON_A3), - PIN(12, SDA2, 0, 15, 0x23, 0x70, + PIN(12, SDA2, 0, 9, 0x23, 0x70, SDA2, DMIC3_DAT_R, I2SO1_D6, RES4, RES5, LVTS_SDI, DBG_MON_A4), - PIN(13, SCL2, 0, 10, 0x23, 0x70, + PIN(13, SCL2, 0, 4, 0x23, 0x70, SCL2, DMIC4_DAT_R, I2SO1_D7, RES4, RES5, RES6, DBG_MON_A5), - PIN(14, SDA3, 0, 16, 0x23, 0x70, + PIN(14, SDA3, 0, 10, 0x23, 0x70, SDA3, DMIC3_DAT, TDMIN_MCK, RES4, RES5, RES6, DBG_MON_A6), - PIN(15, SCL3, 0, 11, 0x23, 0x70, + PIN(15, SCL3, 0, 5, 0x23, 0x70, SCL3, DMIC3_CLK, TDMIN_DI, RES4, RES5, RES6, DBG_MON_A7), - PIN(16, SDA4, 0, 17, 0x23, 0x70, + PIN(16, SDA4, 0, 11, 0x23, 0x70, SDA4, DMIC4_DAT, TDMIN_LRCK, RES4, RES5, RES6, DBG_MON_A8), - PIN(17, SCL4, 0, 12, 0x23, 0x70, + PIN(17, SCL4, 0, 6, 0x23, 0x70, SCL4, DMIC4_CLK, TDMIN_BCK, RES4, RES5, RES6, DBG_MON_A9), PIN(18, DPTX_HPD, 0, 5, 0x10, 0x60, @@ -170,10 +170,10 @@ PIN(43, PWRAP_SPI_MI, 0, 9, 0x21, 0xb0, PWRAP_SPI0_MI, PWRAP_SPI0_MO, SPIM3_MI, RES4, RES5, RES6, DBG_MON_B1), - PIN(44, SPMI_M_SCL, 0, 20, 0x21, 0xb0, + PIN(44, SPMI_M_SCL, 0, 21, 0x21, 0xb0, SPMI_M_SCL, I2SI00_DATA1, SCL5, UTXD5, RES5, RES6, DBG_MON_B2), - PIN(45, SPMI_M_SDA, 0, 21, 0x21, 0xb0, + PIN(45, SPMI_M_SDA, 0, 22, 0x21, 0xb0, SPMI_M_SDA, I2SI00_DATA2, SDA5, URXD5, RES5, RES6, DBG_MON_B3), PIN(46, I2SIN_MCK, 0, 18, 0x21, 0xa0, @@ -329,43 +329,43 @@ PIN(96, DGI_CK, 1, 0, 0x22, 0x60, DGI_CK, DPI_CK, URXD2, I2SO5_MCK, I2SIN_D2, CCU0_JTAG_TRST, RES7), - PIN(97, DISP_PWM0, 0, 20, 0x22, 0x70, + PIN(97, DISP_PWM0, 0, 0, 0x22, 0x70, DISP_PWM0, DVFSRC_EXT_REQ, RES3, RES4, RES5, RES6, RES7), - PIN(98, UART0_TXD, 0, 28, 0x22, 0x70, + PIN(98, UART0_TXD, 0, 4, 0x22, 0x70, UTXD0, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(99, UART0_RXD, 0, 27, 0x22, 0x70, + PIN(99, UART0_RXD, 0, 3, 0x22, 0x70, URXD0, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(100, UART1_RTS, 0, 30, 0x22, 0x70, + PIN(100, UART1_RTS, 0, 6, 0x22, 0x70, URTS1, DSI_TE, I2SO1_D8, KPROW2, PWM_0, TP_URTS1_AO, I2SIN_D0), - PIN(101, UART1_CTS, 0, 29, 0x22, 0x70, + PIN(101, UART1_CTS, 0, 5, 0x22, 0x70, UCTS1, DSI1_TE, I2SO1_D9, KPCOL2, PWM_1, TP_UCTS1_AO, I2SIN_D1), - PIN(102, UART1_TXD, 0, 0, 0x22, 0x70, + PIN(102, UART1_TXD, 0, 8, 0x22, 0x70, UTXD1, VBUSVALID_2P, I2SO1_D10, SSPM_UTXD_AO, TP_UTXD1_AO, MD32_1_TXD, I2SIN_D2), - PIN(103, UART1_RXD, 0, 31, 0x22, 0x70, + PIN(103, UART1_RXD, 0, 7, 0x22, 0x70, URXD1, VBUSVALID_3P, I2SO1_D11, SSPM_URXD_AO, TP_URXD1_AO, MD32_1_RXD, I2SIN_D3), - PIN(104, KPROW0, 1, 25, 0x22, 0x60, + PIN(104, KPROW0, 1, 22, 0x22, 0x60, KPROW0, DISP_PWM1, RES3, RES4, RES5, RES6, RES7), - PIN(105, KPROW1, 1, 26, 0x22, 0x60, + PIN(105, KPROW1, 1, 23, 0x22, 0x60, KPROW1, EDP_TX_HPD, PWM_2, RES4, RES5, RES6, RES7), - PIN(106, KPCOL0, 1, 23, 0x22, 0x60, + PIN(106, KPCOL0, 1, 20, 0x22, 0x60, KPCOL0, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(107, KPCOL1, 1, 24, 0x22, 0x60, + PIN(107, KPCOL1, 1, 21, 0x22, 0x60, KPCOL1, DSI1_TE, PWM_3, SCP_SCL3, I2SIN_MCK, RES6, RES7), - PIN(108, DSI_LCM_RST, 0, 22, 0x22, 0x70, + PIN(108, DSI_LCM_RST, 0, 2, 0x22, 0x70, LCM_RST, KPCOL1, RES3, SCP_SDA3, I2SIN_BCK, RES6, RES7), - PIN(109, DSI_DSI_TE, 0, 21, 0x22, 0x70, + PIN(109, DSI_DSI_TE, 0, 1, 0x22, 0x70, DSI_TE, I2SIN_D3, RES3, RES4, I2SIN_WS, RES6, RES7), PIN(110, MSDC1_CMD, 1, 1, 0x14, 0x20, @@ -421,52 +421,52 @@ PIN(127, EMMC_DSL, 1, 10, 0x25, 0x50, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, RES7), - PIN(128, USB_IDDIG, 0, 3, 0x22, 0x70, + PIN(128, USB_IDDIG, 0, 11, 0x22, 0x70, IDDIG, UCTS2, UTXD5, UFS_MPHY_SCL, mbistreaden_trigger, MD32_1_GPIO0, SCP_SCL2), - PIN(129, USB_DRV_VBUS, 0, 1, 0x22, 0x70, + PIN(129, USB_DRV_VBUS, 0, 9, 0x22, 0x70, SB_DRVVBUS, URTS2, URXD5, UFS_MPHY_SDA, mbistwriteen_trigger, MD32_1_GPIO1, SCP_SDA2), - PIN(130, USB_IDDIG_1P, 0, 4, 0x22, 0x70, + PIN(130, USB_IDDIG_1P, 0, 12, 0x22, 0x70, IDDIG_1P, SPINOR_IO2, SNFI_WP, VPU_UDI_NTRST, RES5, RES6, RES7), - PIN(131, USB_DRV_VBUS_1P, 0, 2, 0x22, 0x70, + PIN(131, USB_DRV_VBUS_1P, 0, 10, 0x22, 0x70, USB_DRVVBUS_1P, SPINOR_IO3, SNFI_HOLD, MD32_1_JTAG_TRST, SCP_JTAG0_TRSTN, APU_JTAG_TRST, RES7), - PIN(132, SPIM0_CSB, 0, 13, 0x25, 0x60, + PIN(132, SPIM0_CSB, 0, 1, 0x25, 0x60, SPIM0_CSB, SCP_SPI0_CS, SPIS0_CSB, VPU_UDI_TMS, RES5, I2SO5_D0, RES7), - PIN(133, SPIM0_CLK, 0, 12, 0x25, 0x60, + PIN(133, SPIM0_CLK, 0, 0, 0x25, 0x60, SPIM0_CLK, SCP_SPI0_CK, SPIS0_CLK, VPU_UDI_TCK, RES5, I2SO5_BCK, RES7), - PIN(134, SPIM0_MO, 0, 15, 0x25, 0x60, + PIN(134, SPIM0_MO, 0, 3, 0x25, 0x60, SPIM0_MO, SCP_SPI0_MO, SPIS0_SI, VPU_UDI_TDO, RES5, I2SO5_WS, RES7), - PIN(135, SPIM0_MI, 0, 14, 0x25, 0x60, + PIN(135, SPIM0_MI, 0, 2, 0x25, 0x60, SPIM0_MI, SCP_SPI0_MI, SPIS0_SO, VPU_UDI_TDI, RES5, I2SO5_MCK, RES7), - PIN(136, SPIM1_CSB, 0, 13, 0x21, 0xb0, + PIN(136, SPIM1_CSB, 0, 14, 0x21, 0xb0, SPIM1_CSB, SCP_SPI1_A_CS, SPIS1_CSB, MD32_1_JTAG_TMS, SCP_JTAG0_TMS, APU_JTAG_TMS, DBG_MON_A15), - PIN(137, SPIM1_CLK, 0, 12, 0x21, 0xb0, + PIN(137, SPIM1_CLK, 0, 13, 0x21, 0xb0, SPIM1_CLK, SCP_SPI1_A_CK, SPIS1_CLK, MD32_1_JTAG_TCK, SCP_JTAG0_TCK, APU_JTAG_TCK, DBG_MON_A14), - PIN(138, SPIM1_MO, 0, 15, 0x21, 0xb0, + PIN(138, SPIM1_MO, 0, 16, 0x21, 0xb0, SPIM1_MO, SCP_SPI1_A_MO, SPIS1_SI, MD32_1_JTAG_TDO, SCP_JTAG0_TDO, APU_JTAG_TDO, DBG_MON_A16), - PIN(139, SPIM1_MI, 0, 14, 0x21, 0xb0, + PIN(139, SPIM1_MI, 0, 15, 0x21, 0xb0, SPIM1_MI, SCP_SPI1_A_MI, SPIS1_SO, MD32_1_JTAG_TDI, SCP_JTAG0_TDI, APU_JTAG_TDI, DBG_MON_A17), - PIN(140, SPIM2_CSB, 0, 17, 0x21, 0xb0, + PIN(140, SPIM2_CSB, 0, 18, 0x21, 0xb0, SPIM2_CSB, SPINOR_CS, SNFI_CS, DMIC3_DAT, RES5, RES6, DBG_MON_A11), - PIN(141, SPIM2_CLK, 0, 16, 0x21, 0xb0, + PIN(141, SPIM2_CLK, 0, 17, 0x21, 0xb0, SPIM2_CLK, SPINOR_CK, SNFI_CLK, DMIC3_CLK, RES5, RES6, DBG_MON_A10), - PIN(142, SPIM2_MO, 0, 19, 0x21, 0xb0, + PIN(142, SPIM2_MO, 0, 20, 0x21, 0xb0, SPIM2_MO, SPINOR_IO0, SNFI_MOSI, DMIC4_DAT, RES5, RES6, DBG_MON_A12), - PIN(143, SPIM2_MI, 0, 18, 0x21, 0xb0, + PIN(143, SPIM2_MI, 0, 19, 0x21, 0xb0, PIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK, RES5, RES6, DBG_MON_A13), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2021