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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120620):
https://review.coreboot.org/c/coreboot/+/52800/comment/b080f7b9_8a32cbf6
PS25, Line 903: else
suspect code indent for conditional statements (16, 8)
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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/3104afbe_1b6848f4
PS20, Line 847: print_me_fw_version
> > The heci_reset will cause problems if the ME is disabled, so even if we move it, we'd have to chan […]
If the ME is enabled, and we want to disable it, we don't want to reset heci. It wont cover that.
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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/7dd05cd4_af1c4786
PS20, Line 847: print_me_fw_version
> The heci_reset will cause problems if the ME is disabled, so even if we move it, we'd have to change the print_fw to stop that running. PCI device disappears and bars stop working.
'if (!is_cse_enabled())' should cover that.
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52800
to look at the new patch set (#25).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Add ME_STATE_BY_CMOS, that will disable the Intel ME.
Message is only sent if me_state is set to 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 79 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/25
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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 24:
(3 comments)
File src/soc/intel/common/block/cse/cse.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120619):
https://review.coreboot.org/c/coreboot/+/52800/comment/af7cb164_b9eff732
PS24, Line 870: if (CONFIG(ME_STATE_BY_CMOS))
that open brace { should be on the previous line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120619):
https://review.coreboot.org/c/coreboot/+/52800/comment/d0dca0f0_ee806247
PS24, Line 901: if (CONFIG(ME_STATE_BY_CMOS))
that open brace { should be on the previous line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120619):
https://review.coreboot.org/c/coreboot/+/52800/comment/7dcbcd0c_d959611e
PS24, Line 905: else
suspect code indent for conditional statements (16, 8)
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Change subject: src/mainboard: Add Star Labs labtop series
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/starlabs/labtop/variants/cml/romstage.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120618):
https://review.coreboot.org/c/coreboot/+/55128/comment/5a43f98b_143d51d9
PS9, Line 115: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
line over 96 characters
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Change subject: amdfwtool: Add a function to extract firmwares
......................................................................
Patch Set 12:
(1 comment)
File util/amdfwtool/extract.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120613):
https://review.coreboot.org/c/coreboot/+/54901/comment/2cd87e21_38cd2052
PS12, Line 91: close (mod_fd);
space prohibited between function name and open parenthesis '('
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52800
to look at the new patch set (#24).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Add ME_STATE_BY_CMOS, that will disable the Intel ME.
Message is only sent if me_state is set to 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 81 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/24
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