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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52800
to look at the new patch set (#24).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Add ME_STATE_BY_CMOS, that will disable the Intel ME.
Message is only sent if me_state is set to 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 81 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/24
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Change subject: cbfstool: Print out the CBFS offset and size
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Patch Set 2:
(1 comment)
File util/cbfstool/cbfstool.c:
https://review.coreboot.org/c/coreboot/+/55158/comment/fe8c140a_729c0d4f
PS2, Line 1507: printf("cbfs_start: 0x%lx\n", image.buffer.offset);
: printf("cbfs_size: 0x%lx\n", image.buffer.size);
Is it ugly?
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Change subject: soc/intel/alderlake: Add new memory parts for ADL boards
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt:
https://review.coreboot.org/c/coreboot/+/54950/comment/76db1f2d_3cebe337
PS2, Line 6: MT53E1G32D2NP-046 WT:B,lp4x-spd-1.hex
> Looks like the part attributes added for `MT53E1G32D2NP-046 WT:B` used wrong # of ranks. […]
Done
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Change subject: util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55000/comment/3a25d720_e514e9d4
PS1, Line 9: Correct the attributes ranksPerChannel as 2 for LP4x global config.
> oh, it will change this value encodeModuleOrganization. never mind... you can ignore my comment.
Ack
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