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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 21:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/dd9e7aaf_c51113e0
PS20, Line 103: struct enable_command {
: struct mkhi_hdr hdr;
: } __packed;
> what is there to pack ?
Fair point!
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52800
to look at the new patch set (#22).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Add ME_STATE_BY_CMOS, that will disable the Intel ME.
Message is only sent if me_state is set to 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 75 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/22
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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 20:
(2 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/b3845b39_38175c3a
PS20, Line 98: int enable_me(void)
> blank line after previous function's ending `}`
Done
https://review.coreboot.org/c/coreboot/+/52800/comment/8342e3a5_742b7bc9
PS20, Line 871: #if CONFIG(ME_STATE_BY_CMOS)
> `if (CONFIG(ME_STATE_BY_CMOS))`
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52800
to look at the new patch set (#21).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Add ME_STATE_BY_CMOS, that will disable the Intel ME.
Message is only sent if me_state is set to 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 78 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/21
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Change subject: ec: Add Star Labs ITE 8987E support
......................................................................
Patch Set 12:
(3 comments)
File src/ec/starlabs/it8987/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/52797/comment/8cb6a381_1c7739fb
PS12, Line 373:
: // Method(_Q45) // SMM Mode - Not used in coreboot
: // {
: // SMB2 = 0xC1
: // }
> remove?
Plan to use it in the future - hence it being left
File src/ec/starlabs/it8987/acpi/hid.asl:
PS12:
> just in general, why keep all of these commented-out lines?
Reminder of the original source I guess. It's been happy for months now so it can go.
https://review.coreboot.org/c/coreboot/+/52797/comment/2f311446_996405b4
PS12, Line 16: // If (((OSYS >= 0x07DD) && (HEFE == One)))
> remove?
Removed
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Hello build bot (Jenkins), Andy Pont, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52797
to look at the new patch set (#13).
Change subject: ec: Add Star Labs ITE 8987E support
......................................................................
ec: Add Star Labs ITE 8987E support
Support for Star Labs labtop series EC
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6
---
A src/ec/starlabs/it8987/Kconfig
A src/ec/starlabs/it8987/Makefile.inc
A src/ec/starlabs/it8987/acpi/ac.asl
A src/ec/starlabs/it8987/acpi/battery.asl
A src/ec/starlabs/it8987/acpi/cmos.asl
A src/ec/starlabs/it8987/acpi/ec.asl
A src/ec/starlabs/it8987/acpi/hid.asl
A src/ec/starlabs/it8987/acpi/keyboard.asl
A src/ec/starlabs/it8987/acpi/lid.asl
A src/ec/starlabs/it8987/acpi/thermal.asl
A src/ec/starlabs/it8987/chip.h
A src/ec/starlabs/it8987/ec.c
A src/ec/starlabs/it8987/ec.h
13 files changed, 1,083 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/52797/13
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Change subject: soc/mediatek/mt8195: Enable mt8195 auxadc
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
File src/soc/mediatek/mt8195/Makefile.inc has one or more executable bits set in the file permissions.
File src/soc/mediatek/mt8195/include/soc/addressmap.h has one or more executable bits set in the file permissions.
File src/soc/mediatek/mt8195/include/soc/auxadc.h has one or more executable bits set in the file permissions.
File src/soc/mediatek/mt8195/include/soc/efuse.h has one or more executable bits set in the file permissions.
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Change subject: cpu/x86/mp_init: Support both xapic and x2apic with common code
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Checked x2apic mode, it's working fine. Can you check it in apic mode?
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