coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: mb/google/cherry: Get RAM code from ADC
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55156 ) Change subject: mb/google/cherry: Get RAM code from ADC ...................................................................... mb/google/cherry: Get RAM code from ADC On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Cherry the RAM code can be read from ADC channel 2 and 3. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9 --- M src/mainboard/google/cherry/boardid.c 1 file changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/55156/1 diff --git a/src/mainboard/google/cherry/boardid.c b/src/mainboard/google/cherry/boardid.c index 34d7692..a51eee8 100644 --- a/src/mainboard/google/cherry/boardid.c +++ b/src/mainboard/google/cherry/boardid.c @@ -1,8 +1,66 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> + +#define ADC_LEVELS 12 + +enum { + /* RAM IDs */ + RAM_ID_HIGH_CHANNEL = 3, + RAM_ID_LOW_CHANNEL = 2, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_HIGH_CHANNEL] = ram_voltages, + [RAM_ID_LOW_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} uint32_t ram_code(void) { - return 0; + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) { + cached_ram_code = (get_adc_index(RAM_ID_HIGH_CHANNEL) << 4 | + get_adc_index(RAM_ID_LOW_CHANNEL)); + printk(BIOS_DEBUG, "RAM Code: %#02x\n", cached_ram_code); + } + + return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/55156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f28bc1c567cb886bd90d930219981a6206b9bb9 Gerrit-Change-Number: 55156 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Enable mt8195 auxadc
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55155 ) Change subject: soc/mediatek/mt8195: Enable mt8195 auxadc ...................................................................... soc/mediatek/mt8195: Enable mt8195 auxadc Enable auxadc on MediaTek mt8195 platform. Signed-off-by: Zhiqiang Ma <zhiqiang.ma(a)mediatek.com> Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/auxadc.h A src/soc/mediatek/mt8195/include/soc/efuse.h 4 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/55155/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc old mode 100644 new mode 100755 index 3bdb47c..e053638 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) +bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c @@ -12,6 +13,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c +verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-y += ../common/i2c.c i2c.c @@ -20,6 +22,7 @@ verstage-y += ../common/uart.c verstage-y += ../common/wdt.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += ../common/clkbuf.c romstage-y += ../common/dram_init.c @@ -44,6 +47,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c +ramstage-y += ../common/auxadc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h old mode 100644 new mode 100755 index e5195ca..5d5c937 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -50,7 +50,7 @@ DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, - AUXADC_BASE = IO_PHYS + 0x01001000, + AUXADC_BASE = IO_PHYS + 0x01002000, UART0_BASE = IO_PHYS + 0x01001100, PERICFG_AO_BASE = IO_PHYS + 0x01003000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8195/include/soc/auxadc.h b/src/soc/mediatek/mt8195/include/soc/auxadc.h new file mode 100755 index 0000000..f697831 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/auxadc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_H +#define _MTK_ADC_H + +#include <soc/auxadc_common.h> +#include <soc/infracfg.h> +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8195_infracfg_ao_regs *const mtk_infracfg = mt8195_infracfg_ao; + +#endif diff --git a/src/soc/mediatek/mt8195/include/soc/efuse.h b/src/soc/mediatek/mt8195/include/soc/efuse.h new file mode 100755 index 0000000..b746170 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t rserved[130]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x208); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79420e20c9ed6155791b490e1b5e4b44a579a49 Gerrit-Change-Number: 55155 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: psp_verstage: initialize i2c in soc_init
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55136 ) Change subject: psp_verstage: initialize i2c in soc_init ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: LGTM. Thanks Kangheui! -- To view, visit https://review.coreboot.org/c/coreboot/+/55136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Gerrit-Change-Number: 55136 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 05:20:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: add SPM loader
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55140 ) Change subject: soc/mediatek/mt8195: add SPM loader ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Gerrit-Change-Number: 55140 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 05:19:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: add SPM loader
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, DAWEI CHIEN, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55140 to look at the new patch set (#6). Change subject: soc/mediatek/mt8195: add SPM loader ...................................................................... soc/mediatek/mt8195: add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. This adds 43ms to the boot time. TEST=program counter of SPM is correct value after booting up. Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Signed-off-by: Dawei Chien <dawei.chien(a)mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/spm.h A src/soc/mediatek/mt8195/spm.c 4 files changed, 1,155 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/55140/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0f9b9f86e44b293c1cc47213946304c64aea75e Gerrit-Change-Number: 55140 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cezanne/psp_verstage: add reset/timer svc
by Kangheui Won (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55137 to look at the new patch set (#4). Change subject: cezanne/psp_verstage: add reset/timer svc ...................................................................... cezanne/psp_verstage: add reset/timer svc The new cezanne PSP release added support for these svcs. So add those functionality back to cezanne psp_verstage. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 --- M src/soc/amd/cezanne/psp_verstage/chipset.c M src/soc/amd/cezanne/psp_verstage/svc.c M src/soc/amd/common/psp_verstage/Makefile.inc M src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h 4 files changed, 55 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/55137/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0 Gerrit-Change-Number: 55137 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: psp_verstage: initialize i2c in soc_init
by Kangheui Won (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55136 to look at the new patch set (#4). Change subject: psp_verstage: initialize i2c in soc_init ...................................................................... psp_verstage: initialize i2c in soc_init GSC is connected with AP via i2c bus so we need to enable i2c in psp_verstage. Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c --- M src/mainboard/google/guybrush/verstage.c M src/mainboard/google/zork/verstage.c M src/soc/amd/common/psp_verstage/fch.c 3 files changed, 6 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/55136/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c Gerrit-Change-Number: 55136 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP] cpu/x86: Add Kconfig X2APIC SUPPORT
by Wonkyu Kim (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Kyösti Mälkki. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55073 ) Change subject: [WIP] cpu/x86: Add Kconfig X2APIC_SUPPORT ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Checking x2APIC mode is also in asembly code. if we want to use Kconfig, we also need to change it. For detail, refer https://review.coreboot.org/c/coreboot/+/52696/6/src/cpu/x86/smm/smm_stub.S -- To view, visit https://review.coreboot.org/c/coreboot/+/55073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f Gerrit-Change-Number: 55073 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 05:05:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [Do Not Merge] Turn on UART in Kconfig temporary
by Wonkyu Kim (Code Review) 03 Jun '21

03 Jun '21

Wonkyu Kim has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28968 ) Change subject: [Do Not Merge] Turn on UART in Kconfig temporary ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fb730302a7750c2410eb11289461de2529c5386 Gerrit-Change-Number: 28968 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: [TEST]3rdparty/vboot: Vboot version update
by Wonkyu Kim (Code Review) 03 Jun '21

03 Jun '21

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39447 ) Change subject: [TEST]3rdparty/vboot: Vboot version update ...................................................................... [TEST]3rdparty/vboot: Vboot version update Update Vboot version to bb6c23472a0f to fix depthcharge build Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39447/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 5059062..bb6c234 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 5059062dd352e3864fb68f8a061e87bd7055d12a +Subproject commit bb6c23472a0fd0565b3991331b63a4ed319d7872 -- To view, visit https://review.coreboot.org/c/coreboot/+/39447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe5d13fff9730229818cd2201c55b794ba69c5ea Gerrit-Change-Number: 39447 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021