coreboot-gerrit June 2021

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Change in coreboot[master]: mb/lenovo/t410: Update PCH PCIe RP comments
by Swift Geek (Sebastian Grzywna) (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Swift Geek (Sebastian Grzywna) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55171 ) Change subject: mb/lenovo/t410: Update PCH PCIe RP comments ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Gerrit-Change-Number: 55171 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 17:01:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports
by Swift Geek (Sebastian Grzywna) (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Swift Geek (Sebastian Grzywna) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: To make it more clear to anyone having the device on hand: J22 - WWAN slot (a slot with connection to UIM/SIM card slot) - Located on the same side as docking connector J27 - WUSB slot (UWB led signal is pretty much the only thing that makes it special) J32 - WLAN slot (a slot with controller link connection for intel wifi) - Located the closest to the CPU socket -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:58:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55170 ) Change subject: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55170/comment/d7f67be6_6ef209ee PS2, Line 121: .i2c[4] = { : .speed = I2C_SPEED_FAST, : }, Drop this too? -- To view, visit https://review.coreboot.org/c/coreboot/+/55170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Gerrit-Change-Number: 55170 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:54:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled
by Subrata Banik (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55170 ) Change subject: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55170/comment/68207975_59cd493a PS1, Line 8: > Why this change is desired wasn't obvious to me. I'd add the following: […] Thanks Angel -- To view, visit https://review.coreboot.org/c/coreboot/+/55170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Gerrit-Change-Number: 55170 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled
by Subrata Banik (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Hello Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55170 to look at the new patch set (#2). Change subject: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled ...................................................................... mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled I2C4 is not used on Brya. Thus, disable it in SerialIoI2cMode. TEST=Make sure FSP is not programming I2C4. Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/55170/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Gerrit-Change-Number: 55170 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Looks like the comments show the mapping on preproduction boards [old], and production boards use a […] Did CB:55171 to update the comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:49:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cbfstool: Print out the CBFS offset and size
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Bao Zheng, Zheng Bao. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55158 ) Change subject: cbfstool: Print out the CBFS offset and size ...................................................................... Patch Set 2: (1 comment) File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/55158/comment/ff51e8c2_e271412b PS2, Line 1507: printf("cbfs_start: 0x%lx\n", image.buffer.offset); : printf("cbfs_size: 0x%lx\n", image.buffer.size); > > Is it ugly? […] There is already support for printing the offset of CBFS using `cbfstool FILE layout`. It prints out the offsets of all sections in the FILE. Can that be used for your purpose instead of adding cbfs_start:/cbfs_size: here? -- To view, visit https://review.coreboot.org/c/coreboot/+/55158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb7f55180cecfcb7526cf5ae94741b6ae526b66 Gerrit-Change-Number: 55158 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 03 Jun 2021 16:48:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55170 ) Change subject: mb/google/brya: Set SerialIoI2cMode for I2C4 as PchSerialIoDisabled ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55170/comment/d8d0f917_8e7caf0a PS1, Line 8: Why this change is desired wasn't obvious to me. I'd add the following: I2C4 is not used on Brya. Thus, disable it in SerialIoI2cMode. -- To view, visit https://review.coreboot.org/c/coreboot/+/55170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9 Gerrit-Change-Number: 55170 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:47:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Tim Wawrzynczak (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/b0ce5e6f_fdb8f314 PS1, Line 206: PXSX > @Tim: Once the change lands, you will have to update Intel platforms to expose the _DSD property und […] SG will do, Raul can you point me at the patch once you pull it in, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Jun 2021 16:44:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Update PCH PCIe RP comments
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55171 ) Change subject: mb/lenovo/t410: Update PCH PCIe RP comments ...................................................................... mb/lenovo/t410: Update PCH PCIe RP comments Looks like the comments were derived from a preproduction board's schematics. Production boards use a different port mapping. Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/55171/1 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 5f167df..4d10508 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -71,11 +71,11 @@ subsystemid 0x17aa 0x215e end - device pci 1c.0 on end # PCIe Port #1 (wlan) - device pci 1c.1 off end # PCIe Port #2 (wwan) - device pci 1c.2 off end # PCIe Port #3 (wusb) - device pci 1c.3 on end # PCIe Port #4 (ExpressCard) - device pci 1c.4 on + device pci 1c.0 on end # PCIe Port #1: WWAN mPCIe slot + device pci 1c.1 off end # PCIe Port #2: WLAN mPCIe slot + device pci 1c.2 off end # PCIe Port #3: WUSB mPCIe slot + device pci 1c.3 on end # PCIe Port #4: ExpressCard + device pci 1c.4 on # PCIe Port #5: Ricoh SD & FireWire subsystemid 0x17aa 0x2133 chip drivers/ricoh/rce822 register "sdwppol" = "1" @@ -84,10 +84,10 @@ subsystemid 0x17aa 0x2134 end end - end # PCIe Port #5 (Ricoh SD & FW) - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 Intel Gigabit Ethernet PHY (not PCIe) + end + device pci 1c.5 off end # PCIe Port #6: Intel GbE PHY (not PCIe) + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 -- To view, visit https://review.coreboot.org/c/coreboot/+/55171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Gerrit-Change-Number: 55171 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2021