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Change subject: mb/google/guybrush: Override I2C3 pad configuration
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55149/comment/d34cba71_58ccd094
PS3, Line 7: mb/google/guybrush: Override I2C3 pad configuration
Commit message needs update. SoC code is also being changed. It would be good to capture the details of the SoC change and the motivation behind it.
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Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
......................................................................
Patch Set 6:
(2 comments)
File src/soc/amd/common/block/rtd3/Kconfig:
https://review.coreboot.org/c/coreboot/+/54966/comment/2034f8c9_a9940bbc
PS1, Line 3: default n
> IIRC default is no. If so, we dont need to mention it.
Done
File src/soc/amd/common/block/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/54966/comment/e80c2e63_9252e80e
PS1, Line 210: pci_dev_read_resources
> I'll do that and push up a change.
Done
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Change subject: acpi/device: Add ability to generate proper _STA for PowerResource
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
I refactored it a bit so we actually verify that all the GPIOs are in the correct state.
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Hello build bot (Jenkins), Karthikeyan Ramasubramanian,
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Change subject: mb/google/guybrush: Enable RTD3 support for NVMe
......................................................................
mb/google/guybrush: Enable RTD3 support for NVMe
This will tell the kernel to ignore PCI ASPM when suspending the device
and instead place the device into D3. We don't actually have a pin to
control power to the NVMe so we leave it in D3Hot. I'm not sure if
`PCI_RST#` is working correctly on S0i3 suspend/resume. If it's not
acting as expected we can add the reset GPIO and have the OS do it.
BUG=b:184617186
TEST=Run suspend_stress_test on guybrush for 10 cycles
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I29539ac120a9f1b7c1bfeaca745cfc82acfa461a
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
2 files changed, 8 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/54967/6
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I'd like you to reexamine a change. Please visit
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Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
......................................................................
drivers/pcie/rtd3/device: Add PCIe RTD3 driver
This driver was inspired from soc/intel/common/block/pci/rtd3. I decided
to copy and modify it because the Intel driver has a lot of Intel
specific code.
This driver has been stripped down to only provide a power resource and
set the StorageD3Enable property. This driver is SoC agnostic and does
not handle suspending the actual PCIe root port. That should be
implemented by an SoC specific driver.
This is required for Guybrush to suspend/resume properly because the
NVMe power is tied to the S0 power rails, so the kernel needs to place
the device into D3.
BUG=b:184617186
TEST=Guybrush is able to suspend/resume properly. Also see power
resource get enabled / disabled.
[ 56.075559] power-0416 __acpi_power_off : Power resource [RTD3] turned off
[ 56.075562] device_pm-0279 device_set_power : Device [PXSX] transitioned to D3cold
[ 56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold
[ 56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs
[ 123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4
[ 123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0
[ 123.464982] power-0360 __acpi_power_on : Power resource [RTD3] turned on
[ 123.464984] device_pm-0279 device_set_power : Device [PXSX] transitioned to D0
[ 123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0
---
A src/drivers/pcie/rtd3/device/Kconfig
A src/drivers/pcie/rtd3/device/Makefile.inc
A src/drivers/pcie/rtd3/device/chip.c
A src/drivers/pcie/rtd3/device/chip.h
4 files changed, 204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/54966/6
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Change subject: acpi/device: Add ability to generate proper _STA for PowerResource
......................................................................
acpi/device: Add ability to generate proper _STA for PowerResource
acpi_device_add_power_res currently generates a `_STA` method hardcoded
to ON. This change enables the ability to generate a `_STA` method that
queries the status of the GPIOs to determine if the power resource is ON
or OFF.
BUG=b:184617186
TEST=Dump SSDT table for guybrush
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I91410556db002c620fd9aaa99981457808da93a5
---
M src/acpi/device.c
M src/include/acpi/acpi_device.h
2 files changed, 56 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55027/4
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Change subject: mb/google/guybrush: Override I2C3 pad configuration
......................................................................
mb/google/guybrush: Override I2C3 pad configuration
I2C bus to Google Security Chip (GSC) should be at 1.8V level. By
default, all the I2C buses are initialized to operate at 3.3 V. Override
the I2C3 pad control configuration.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/amd/majolica/devicetree.cb
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/i2c.c
4 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55149/3
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Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration
......................................................................
mb/google/guybrush/var/guybrush: Update GPIO configuration
Some of the GPIOs are either re-purposed for different use-cases or are
unused in upcoming board phase (board version 2). Update the GPIO
configuration accordingly. Here are the GPIOs that are updated:
GPIO Board Id 1 Board Id 2
=============================================
GPIO31 TP183 EN_SPKR
GPIO69 EN_SPKR SD_AUX_REST_L
GPIO70 SD_AUX_RESET_L Unused TP27
GPIO74 RAM_ID_CHAN_SEL Unused TP49
BUG=b:189327557, b:188542649, b:188542497
TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is
detected fine in Board ID 1.
Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
2 files changed, 12 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/55148/3
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
......................................................................
drivers/pcie/rtd3/device: Add PCIe RTD3 driver
This driver was inspired from soc/intel/common/block/pci/rtd3. I decided
to copy and modify it because the Intel driver has a lot of Intel
specific code.
This driver has been stripped down to only provide a power resource and
set the StorageD3Enable property. This driver is SoC agnostic and does
not handle suspending the actual PCIe root port. That should be
implemented by an SoC specific driver.
This is required for Guybrush to suspend/resume properly because the
NVMe power is tied to the S0 power rails, so the kernel needs to place
the device into D3.
BUG=b:184617186
TEST=Guybrush is able to suspend/resume properly. Also see power
resource get enabled / disabled.
[ 56.075559] power-0416 __acpi_power_off : Power resource [RTD3] turned off
[ 56.075562] device_pm-0279 device_set_power : Device [PXSX] transitioned to D3cold
[ 56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold
[ 56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs
[ 123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4
[ 123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0
[ 123.464982] power-0360 __acpi_power_on : Power resource [RTD3] turned on
[ 123.464984] device_pm-0279 device_set_power : Device [PXSX] transitioned to D0
[ 123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0
---
A src/drivers/pcie/rtd3/device/Kconfig
A src/drivers/pcie/rtd3/device/Makefile.inc
A src/drivers/pcie/rtd3/device/chip.c
A src/drivers/pcie/rtd3/device/chip.h
4 files changed, 204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/54966/5
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55027 )
Change subject: acpi/device: Add ability to generate proper _STA for PowerResource
......................................................................
Patch Set 3:
(2 comments)
File src/acpi/device.c:
https://review.coreboot.org/c/coreboot/+/55027/comment/7c6c9ffc_98d181e9
PS2, Line 649: 0x1
> Since a PowerResources uses the return value of _STA differently than a Device, how about adding new […]
Done
File src/include/acpi/acpi_device.h:
https://review.coreboot.org/c/coreboot/+/55027/comment/2c325b6b_ba6eb81a
PS2, Line 459:
: /* Write a _STA method that checks the state of the GPIOs. Otherwise
: * the _STA method will always return _ON.
: */
: bool enable_status;
> that's good, also +1.
Done
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I91410556db002c620fd9aaa99981457808da93a5
Gerrit-Change-Number: 55027
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