Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55132 )
Change subject: mb/google/brya: Create primus variant
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
Hi Tim, can we also submit this CL?
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51838 )
Change subject: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> *ping* […]
I like the idea, but I have no clue about Perl, nor how to write linters.
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Hello build bot (Jenkins), Raul Rangel, Martin Roth, Furquan Shaikh, Eric Peers,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration
......................................................................
mb/google/guybrush/var/guybrush: Update GPIO configuration
Some of the GPIOs are either re-purposed for different use-cases or are
unused in upcoming board phase (board version 2). Update the GPIO
configuration accordingly. Here are the GPIOs that are updated:
GPIO Board Id 1 Board Id 2
=============================================
GPIO31 TP183 EN_SPKR
GPIO69 EN_SPKR SD_AUX_REST_L
GPIO70 SD_AUX_RESET_L Unused TP27
GPIO74 RAM_ID_CHAN_SEL Unused TP49
BUG=b:189327557, b:188542649, b:188542497
TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is
detected fine in Board ID 1.
Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
2 files changed, 14 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/55148/4
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Furquan Shaikh, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55149
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Change subject: soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
......................................................................
soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/amd/majolica/devicetree.cb
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/i2c.c
4 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55149/4
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55149 )
Change subject: mb/google/guybrush: Override I2C3 pad configuration
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55149/comment/bd8293e5_a93b7aed
PS3, Line 55: i2c_pad_ctrl_rx_sel
> Hrmm, it would have been nice to group this with the other i2c config: https://source.chromium. […]
I initially thought about adding it to soc_amd_common_i2c_config. Later I realized that this misc pad config applies only to picasso and cezanne. This register set does not exist in stoneyridge.
Also not sure about moving to dw_i2c_bus_config, since that is used in Intel platforms too and they configure the voltage level differently.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55149 )
Change subject: mb/google/guybrush: Override I2C3 pad configuration
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55149/comment/82e61c40_99102371
PS3, Line 55: i2c_pad_ctrl_rx_sel
Hrmm, it would have been nice to group this with the other i2c config: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
How would we feel about adding a voltage into struct dw_i2c_bus_config?
The other option is we create an AMD specific i2c_bus_config that also contains i2c_scl_reset above. We would need to translate this into a dw_i2c_bus_config in soc_get_i2c_bus_config.
I kind of like this approach because then we can keep all the configuration grouped.
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