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Change subject: soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
......................................................................
soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/amd/majolica/devicetree.cb
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/i2c.c
4 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55149/4
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Hello build bot (Jenkins), Raul Rangel, Martin Roth, Furquan Shaikh, Eric Peers,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration
......................................................................
mb/google/guybrush/var/guybrush: Update GPIO configuration
Some of the GPIOs are either re-purposed for different use-cases or are
unused in upcoming board phase (board version 2). Update the GPIO
configuration accordingly. Here are the GPIOs that are updated:
GPIO Board Id 1 Board Id 2
=============================================
GPIO31 TP183 EN_SPKR
GPIO69 EN_SPKR SD_AUX_REST_L
GPIO70 SD_AUX_RESET_L Unused TP27
GPIO74 RAM_ID_CHAN_SEL Unused TP49
BUG=b:189327557, b:188542649, b:188542497
TEST=Build Guybrush mainboard. Verify Audio is audible and SD card is
detected fine in Board ID 1.
Change-Id: I31523b3e03d2b59577f33eae548747834cfc98aa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/guybrush/gpio.c
2 files changed, 14 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/55148/4
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Change subject: mb/google/guybrush: Override I2C3 pad configuration
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55149/comment/bd8293e5_a93b7aed
PS3, Line 55: i2c_pad_ctrl_rx_sel
> Hrmm, it would have been nice to group this with the other i2c config: https://source.chromium. […]
I initially thought about adding it to soc_amd_common_i2c_config. Later I realized that this misc pad config applies only to picasso and cezanne. This register set does not exist in stoneyridge.
Also not sure about moving to dw_i2c_bus_config, since that is used in Intel platforms too and they configure the voltage level differently.
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Change subject: mb/google/guybrush: Override I2C3 pad configuration
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55149/comment/82e61c40_99102371
PS3, Line 55: i2c_pad_ctrl_rx_sel
Hrmm, it would have been nice to group this with the other i2c config: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…
How would we feel about adding a voltage into struct dw_i2c_bus_config?
The other option is we create an AMD specific i2c_bus_config that also contains i2c_scl_reset above. We would need to translate this into a dw_i2c_bus_config in soc_get_i2c_bus_config.
I kind of like this approach because then we can keep all the configuration grouped.
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Change subject: Documentation: Add proposal to allow enabling serial console with a flag
......................................................................
Patch Set 3:
(1 comment)
File Documentation/technotes/2021-05-selectable-serial-console.md:
https://review.coreboot.org/c/coreboot/+/54385/comment/b48f7400_c124055b
PS1, Line 112: and change the default to whatever is found there.
> I updated the proposal to use a cbfs file (created with cbfstool add-int).
SGTM in general, but you removed the part about forgoing the bootblock now? That part is still important -- remember that non-x86 platforms can't access flash until a lot of other initialization in the bootblock has happened. (Also -- this is just something to keep in mind for the implementation -- you'll need some safeguards to avoid recursion when the CBFS code tries to print things.)
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Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration
......................................................................
Patch Set 3:
(3 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/55148/comment/bd8781bb_09f7cc40
PS3, Line 84: GPIO_70
> Should we do PAD_NC(GPIO_70)?
+1
https://review.coreboot.org/c/coreboot/+/55148/comment/97565739_b1700288
PS3, Line 86: GPIO_74
PAD_NC(GPIO_74)
File src/mainboard/google/guybrush/variants/guybrush/gpio.c:
https://review.coreboot.org/c/coreboot/+/55148/comment/1a8c7032_a4572045
PS1, Line 14: HIGH
> There is some history involved. Initially EN_SPKR was tied to a 3. […]
Aah I see.. Thanks for the explanation Karthik. Since the default for board id 1 changed here, I was curious about the impact.
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Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/55148/comment/219ec24b_2e32f16f
PS3, Line 84: GPIO_70
Should we do PAD_NC(GPIO_70)?
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Change subject: mb/google/guybrush/var/guybrush: Update GPIO configuration
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55148/comment/1bb27a94_cf47ecb9
PS1, Line 14: TP183
> it was unused. Ought to comment as such. https://b.corp.google. […]
Marked it as NC in board ID 1.
https://review.coreboot.org/c/coreboot/+/55148/comment/b3ad3c67_0e52ff6e
PS1, Line 20: TEST=Build Guybrush mainboard.
> probably need a boot board id #1 as well and confirm Speaker and reset are working. […]
Done
File src/mainboard/google/guybrush/variants/guybrush/gpio.c:
https://review.coreboot.org/c/coreboot/+/55148/comment/d96a4b77_c64a18c0
PS1, Line 14: HIGH
> 1. […]
There is some history involved. Initially EN_SPKR was tied to a 3.3 V GPIO whereas the speaker amplifier operates at 1.8 V level. To handle that, a rework was performed and the board version was incremented to identify the boards with that rework.
Later we realized that board version was not the right approach to identify the rework. Hence decided to reclaim the board version 2 for the upcoming hardware build.
So the speaker is enabled by default on boards with or without audio reworks. This is a safe assumption since the rework is done in all the boards (with board ID1).
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