coreboot-gerrit June 2021

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Change in coreboot[master]: 3rdparty/intel-sec-tools: Update to support Boot Guard
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Christopher Meis, Arthur Heymans. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55013 ) Change subject: 3rdparty/intel-sec-tools: Update to support Boot Guard ...................................................................... Patch Set 6: (2 comments) Patchset: PS4: > Had to update the commit again, because the branch in main repo was way behind master branch Does that mean it's now ready to merge? Patchset: PS6: Is this now ready for merge? The comment -- To view, visit https://review.coreboot.org/c/coreboot/+/55013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318 Gerrit-Change-Number: 55013 Gerrit-PatchSet: 6 Gerrit-Owner: Christopher Meis Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christopher Meis Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 01 Jun 2021 05:57:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christopher Meis Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Stefan Reinauer (Code Review) 01 Jun '21

01 Jun '21

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55018 ) Change subject: Documentation/community: Add Discord to forums ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Gerrit-Change-Number: 55018 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 05:55:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Varshit B Pandya (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Patrick Rudolph. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55097 ) Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55097/comment/745146b2_4befc305 PS4, Line 10: Example CL:52013 > I am not allowed to access this URL (404). Done https://review.coreboot.org/c/coreboot/+/55097/comment/8fe7e71e_7d83cda0 PS4, Line 15: TEST=Build and check static.c for consistency > You did this with the next commit, right? yes correct -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 5 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 05:51:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Modify Wifi-SAR sku condition
by Stanley Wu (Code Review) 01 Jun '21

01 Jun '21

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55112 ) Change subject: mb/google/dedede/var/boten: Modify Wifi-SAR sku condition ...................................................................... mb/google/dedede/var/boten: Modify Wifi-SAR sku condition Due to new sku id apply for AMP ALC1015Q-VB. Modify correct WIFI-SAR detect condition for boten/botenflex sku. BUG=b:186174768 TEST=build and test on boten/botenflex Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boten/variant.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/55112/1 diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c index 9afcb27..584ddb6d 100644 --- a/src/mainboard/google/dedede/variants/boten/variant.c +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -30,7 +30,7 @@ { uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id == SKU_ID_BOTENFLEX) + if (sku_id >= SKU_ID_BOTENFLEX) return "wifi_sar-botenflex.hex"; return "wifi_sar-boten.hex"; -- To view, visit https://review.coreboot.org/c/coreboot/+/55112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4fb08e558fee26534564aa5e37cac814c5a98a Gerrit-Change-Number: 55112 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Furquan Shaikh (Code Review) 01 Jun '21

01 Jun '21

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Furquan Shaikh (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Tim Wawrzynczak, Werner Zeh, Kyösti Mälkki. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/55088/comment/c597b2c1_6f2aed99 PS2, Line 834: Now check if there are more speed settings available and report them as well. > The reason I took this approach is that I would like to avoid invalid values being reported. […] Aah okay, that makes sense. The reason I mentioned exposing all possible speeds is because at least the Linux kernel driver uses a least common denominator to choose the appropriate speed to be used for a particular bus i.e. uses the lowest speed value exposed by all devices on the given bus. It would have ensured that the kernel driver gets option to configure for any speeds depending upon the peripheral devices supported. But, what you mentioned about dummy/invalid timings also makes sense. -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 04:56:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century
by Werner Zeh (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Martin Roth, Anand Mistry, Paul Menzel. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55001 ) Change subject: soc/amd/stoneyridge: Set missing RTC offsets for day alarm and century ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/stoneyridge/acpi.c: https://review.coreboot.org/c/coreboot/+/55001/comment/b1feca85_620319b7 PS3, Line 87: fadt->century = 0x32; Hi Could you please have a look at CB:55012 and tell me what you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/55001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1 Gerrit-Change-Number: 55001 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Mistry <amistry(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Anand Mistry <amistry(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 04:53:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Set RTC century byte offset in FADT x86-wide
by Werner Zeh (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Hello Arthur Heymans, build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55012 to look at the new patch set (#2). Change subject: arch/x86: Set RTC century byte offset in FADT x86-wide ...................................................................... arch/x86: Set RTC century byte offset in FADT x86-wide The century byte of the year is stored in CMOS at offset 0x32 for all x86 platforms (done by MC146818 RTC code which is default enabled for x86). This location is not fixed per definition but is established during the past years as 'de facto' standard. This offset is passed into the OS via the ACPI FADT where e.g. Linux uses it if it is set to something != 0. Currently this byte is set differently on all the platforms, either to 0x32 or to 0x0 or even to nothing which results in 0x0. Since this is architecture specific and valid for all the platforms, set this century byte once in the architecture specific code. Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/skylake/fadt.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 23 files changed, 2 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/55012/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Gerrit-Change-Number: 55012 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Furquan Shaikh (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54966/comment/36225f44_9f346535 PS1, Line 9: I decided : to copy and modify it because the Intel driver has a lot of Intel : specific code. > 2. So this is where I grew uncomfortable. I'm not sure of the sequence required to put a PCIe Root Port into D3. We also don't currently support hot plugging support while the root port is in D0. I'm not sure what it would take to support hot plugging while in D3, or if it's even supported by the hardware. The AMD CRB doesn't implement any of this. I think it is the same for Intel platforms too. At least from a hardware design standpoint, we haven't designed these ports for being hot plug capable. But, looks like it was required for the GL9755 SD express device. We can skip this for AMD platforms if you want to wait until it is really required. It would be good to at least track this somehow in case AMD platforms use the same device and run into similar issues. > So I think the Intel driver conflates the two power resources. Your explanation about the two power resources for the root port and the downstream device makes sense. File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/ddb5e287_ee5128cf PS1, Line 210: pci_dev_read_resources > I wasn't a fan of the fake device because it made it difficult to understand. The reasons for the fake/generic device under SoC internal devices have been: 1. Reuse the device/pci* support, scan/enumeration and the device_operations without having to copy the device_operations structure and related function calls in each of these device drivers. 2. Keep the organization in devicetree consistent i.e. the SoC internal devices are never surrounded by any special chip driver. example: drivers/intel/ish, drivers/wifi/generic, soc/intel/common/block/pcie/rtd. > It was confusing why it was writing `acpigen_write_ADR(0);` for the `PXSX`, but then I realized it was the PCI Address of the first device/function on the root port. I think that is primarily to satisfy the assumption in the kernel driver about having a PXSX device. It is not really anything to do with the fake/generic device in coreboot devicetree. > Thoughts? You mentioned that the bridge case can be ignored for now. Though that is fine, I think the problem with duplicating PCI device_operations(i.e. duplicating default_pci_ops_dev) in different device drivers is that it scatters the PCI generic operation structures in different places which can make it difficult to track and perform common changes/fixes. Also, if the drivers/pcie/rtd3/ is supposed to be any kind of PCIe device, then it might have to support all the operations including pci_rom* operations too. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 04:36:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Werner Zeh (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Kyösti Mälkki. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/55088/comment/b366e88b_f13fcc9e PS2, Line 834: Now check if there are more speed settings available and report them as well. > Would it be bad to expose information about all different I2C speeds to the OS? We can skip the ones […] The reason I took this approach is that I would like to avoid invalid values being reported. With the current patch only the timings, that a mainboard explicitly provides in addition to the used one will be reported. This means that the developer needs to be active to add these additional timings where we have a higher chance that they are valid or even were measured to assure their validity. If we apply a generic set of timings, chances are way higher that there will bu "dummy" timings not matching the real hardware very soon. -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 04:29:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2021