coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7125 discussions

Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offsets
by Rex-BC Chen (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offsets ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/5beb661c_0ac6047f PS1, Line 9: Fix GPIO pu/pd offset. > Thanks. Please put this in commit description […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/7025b8c2_cf9a6172 PS4, Line 7: soc/mediatek/mt8195: fix GPIO register offset > Plural: offsets? Done https://review.coreboot.org/c/coreboot/+/55163/comment/ee8d0d0c_cec7bd7a PS4, Line 10: > Where did you get the new values from? Did something not work before and works now? I add document info in commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 06:33:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#115) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M README.md 4 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52260/115 -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 115 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offsets
by Rex-BC Chen (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55163 to look at the new patch set (#5). Change subject: soc/mediatek/mt8195: fix GPIO register offsets ...................................................................... soc/mediatek/mt8195: fix GPIO register offsets Correct the offsets by MT8195 Register Map V0.2-1 chapter: 3.2 GPIO Controller (page 3272) Control register names: PUPD_CFG0 PU_CFG0 Signed-off-by: Zhiqiang Ma <zhiqiang.ma(a)mediatek.com> Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 --- M src/soc/mediatek/mt8195/include/soc/gpio.h 1 file changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55163/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: Add KASAN stubs to coreboot.
by Abdullah Zafar (Code Review) 04 Jun '21

04 Jun '21

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32231 Change subject: Add KASAN stubs to coreboot. ...................................................................... Add KASAN stubs to coreboot. Add option in Kconfig to compile with KASAN. Modify src/lib/Makefile.inc to enable gcc KASAN. Remove lint errors and warnings from kasan.c. Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> Changes to be committed: modified: src/Kconfig modified: src/lib/Makefile.inc new file: src/lib/kasan.c Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 --- M src/Kconfig M src/lib/Makefile.inc A src/lib/kasan.c 3 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32231/1 diff --git a/src/Kconfig b/src/Kconfig index 62b3818..96e746e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -219,6 +219,15 @@ coverage information in CBMEM for extraction from user space. If unsure, say N. +config KASAN + bool "Kernel Address sanitizer support" + default y + help + Instrument the code with checks for UAF and OOB erros. If unsure, + say N because it adds a small performance penalty and may abort + on code that happens to work in spite of the UB. + + config UBSAN bool "Undefined behavior sanitizer support" default n diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..88afaaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,12 @@ CFLAGS_ramstage += -fsanitize=undefined endif +ifeq ($(CONFIG_KASAN),y) +ramstage-y += kasan.c +CFLAGS_ramstage += -fsanitize=kernel-address +endif + + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -83,7 +89,7 @@ romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -romstage-y += ramtest.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c romstage-y += region_file.c diff --git a/src/lib/kasan.c b/src/lib/kasan.c new file mode 100644 index 0000000..3f482e9 --- /dev/null +++ b/src/lib/kasan.c @@ -0,0 +1,29 @@ +#include <stddef.h> + +/* + *Empty stubs for required by gcc to add compiler code + */ +void __asan_handle_no_return(void); +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr, size_t x); +void __asan_storeN_noabort(unsigned long addr, size_t x); + + +void __asan_handle_no_return(void) { } +void __asan_load1_noabort(unsigned long addr) { } +void __asan_store1_noabort(unsigned long addr) { } +void __asan_load2_noabort(unsigned long addr) { } +void __asan_store2_noabort(unsigned long addr) { } +void __asan_load4_noabort(unsigned long addr) { } +void __asan_store4_noabort(unsigned long addr) { } +void __asan_store8_noabort(unsigned long addr) { } +void __asan_load8_noabort(unsigned long addr) { } +void __asan_loadN_noabort(unsigned long addr, size_t i) { } +void __asan_storeN_noabort(unsigned long addr, size_t i) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/32231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id13970514e37dfffb751391fb3e7e6b53ccc7577 Gerrit-Change-Number: 32231 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: TEST ONLY DO NOT SUMMIT
by Paul2 Huang (Code Review) 04 Jun '21

04 Jun '21

Paul2 Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55176 ) Change subject: TEST ONLY DO NOT SUMMIT ...................................................................... Patch Set 1: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie01870e0f3b0259f590cf9d133fab5e763f988a4 Gerrit-Change-Number: 55176 Gerrit-PatchSet: 1 Gerrit-Owner: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 06:10:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: TEST ONLY DO NOT SUMMIT
by Paul2 Huang (Code Review) 04 Jun '21

04 Jun '21

Paul2 Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55176 ) Change subject: TEST ONLY DO NOT SUMMIT ...................................................................... TEST ONLY DO NOT SUMMIT TEST BUG=none BRANCH=none TEST=none Change-Id: Ie01870e0f3b0259f590cf9d133fab5e763f988a4 --- M README.md 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/55176/1 diff --git a/README.md b/README.md index 14879c1..41d9549 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,4 @@ +TEST ONLY coreboot README =============== -- To view, visit https://review.coreboot.org/c/coreboot/+/55176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie01870e0f3b0259f590cf9d133fab5e763f988a4 Gerrit-Change-Number: 55176 Gerrit-PatchSet: 1 Gerrit-Owner: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86: Set RTC century byte offset in FADT x86-wide
by Arthur Heymans (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Werner Zeh, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55012 ) Change subject: arch/x86: Set RTC century byte offset in FADT x86-wide ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: 'for file in $(find -name \*.layout); do grep -l "^400" $file; done' Looks like a lot of mainboards have an option in cmos.layout there... You might want to explicitly set that byte as reserved in there for all boards. You can check that in C code: see for instance soc/intel/xeon_sp/cpx/romstage.c how this is done. -- To view, visit https://review.coreboot.org/c/coreboot/+/55012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Gerrit-Change-Number: 55012 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 06:07:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Hung-Te Lin (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/f99babbe_673a30cb PS1, Line 9: Fix GPIO pu/pd offset. > In file MT8195 Register Map_V0.2 -1.pdf […] Thanks. Please put this in commit description soc/mediatek/mt8195: fix GPIO register offset Correct the offsets by MT8195 Register Map V0.2-1 chapter: 3.2 GPIO Controller (page 3272) Control register names: PUPD_CFG0 PU_CFG0 -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/bc317dcc_d85b6d3a PS4, Line 7: soc/mediatek/mt8195: fix GPIO register offset Plural: offsets? https://review.coreboot.org/c/coreboot/+/55163/comment/552895e2_4f684b2a PS4, Line 10: Where did you get the new values from? Did something not work before and works now? -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55089 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Gerrit-Change-Number: 55089 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:57:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021