June 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
by Werner Zeh (Code Review) June 3, 2021

June 3, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54960 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 63 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index dde0e9b..fa82a68 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -12,11 +12,21 @@ register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" + # Enable heci1 communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "Heci2Enable" = "1" + # Display related UPDs + # Enable HPD for DDI ports C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports C + register "DdiPortCDdc" = "1" + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" @@ -104,6 +114,10 @@ # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 5c25e95..88e7d06 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,18 +15,6 @@ #include <soc/soc_chip.h> #include <string.h> -/* - * ME End of Post configuration - * 0 - Disable EOP. - * 1 - Send in PEI (Applicable for FSP in API mode) - * 2 - Send in DXE (Not applicable for FSP in API mode) - */ -enum { - EOP_DISABLE, - EOP_PEI, - EOP_DXE, -} EndOfPost; - static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -111,12 +99,60 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { + struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; + struct soc_intel_elkhartlake_config *config = config_of_soc(); /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); - /* TODO: Update with UPD override as FSP matures */ + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); + + /* Display config */ + params->DdiPortAHpd = config->DdiPortAHpd; + params->DdiPortADdc = config->DdiPortADdc; + params->DdiPortCHpd = config->DdiPortCHpd; + params->DdiPortCDdc = config->DdiPortCDdc; + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosLock = 0; + params->PchLockDownBiosInterface = 0; + params->PchWriteProtectionEnable[0] = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosLock = 1; + params->PchLockDownBiosInterface = 1; + params->PchWriteProtectionEnable[0] = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } + + /* Disable PAVP */ + params->PavpEnable = 0; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = 1; + + /* PCH Master Gating Control */ + params->PchPostMasterClockGating = 1; + params->PchPostMasterPowerGating = 1; + + /* HECI */ + params->Heci3Enabled = config->Heci3Enable; /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 15 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/storo: Modify I2C times for touchpad
by Werner Zeh (Code Review) June 3, 2021

June 3, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55109 ) Change subject: mb/google/dedede/var/storo: Modify I2C times for touchpad ...................................................................... mb/google/dedede/var/storo: Modify I2C times for touchpad Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately (380<frequency<400 kHz). Measured touchpad I2C frequency is 394 kHz BUG=b:189740533 BRANCH=dedede TEST=Build bios and make sure frequency meets specification. Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55109 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 40b17df..6336192 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -26,8 +26,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 125, - .fall_time_ns = 19, + .rise_time_ns = 260, + .fall_time_ns = 50, }, .i2c[1] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/55109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Gerrit-Change-Number: 55109 Gerrit-PatchSet: 2 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add PMC ACPI interface
by EricR Lai (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55172 ) Change subject: soc/intel/alderlake: Add PMC ACPI interface ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0 Gerrit-Change-Number: 55172 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:32:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/storo: Update gpio setting
by Tao Xia (Code Review) June 3, 2021

June 3, 2021

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55175 ) Change subject: mb/google/dedede/var/storo: Update gpio setting ...................................................................... mb/google/dedede/var/storo: Update gpio setting Correct GPIO settings as below reason: 1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF. 2. GPP_B7 should configure as WWAN SAR detect ODL, but set to GPI BUG=b:188956448 BRANCH=dedede TEST=The LTE DPR pin can be pulled down normally when someone get close to the P-sensor antenna. Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Idc214fcd9c4631368a71f4d59bb644df739982ab --- M src/mainboard/google/dedede/variants/storo/gpio.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/55175/1 diff --git a/src/mainboard/google/dedede/variants/storo/gpio.c b/src/mainboard/google/dedede/variants/storo/gpio.c index 3d830e7..a73caf5 100644 --- a/src/mainboard/google/dedede/variants/storo/gpio.c +++ b/src/mainboard/google/dedede/variants/storo/gpio.c @@ -8,14 +8,20 @@ /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), - /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ - PAD_CFG_GPI_IRQ_WAKE(GPP_B7, NONE, DEEP, LEVEL, INVERT), + /* B7 : WWAN_SAR_DETECT_R_ODL */ + PAD_CFG_GPO(GPP_B7, 1, DEEP), /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), /* D15 : EN_PP3300_CAMERA */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), /* D22 : AP_I2C_SUB_SDA*/ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* D23 : AP_I2C_SUB_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc214fcd9c4631368a71f4d59bb644df739982ab Gerrit-Change-Number: 55175 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]amdfwtool: Add a script to replace AMD firmware
by build bot (Jenkins) (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55160 ) Change subject: [WIP]amdfwtool: Add a script to replace AMD firmware ...................................................................... Patch Set 3: (4 comments) File util/amdfwtool/replace.sh: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/18fc600f_6045565c PS3, Line 12: CBFS_ADDRESS=$(eval $CBFSTOOL $IMAGE layout | grep "^'COREBOOT'" | sed "s/'COREBOOT' (CBFS, size [0-9]\+, offset $[0-9]\+$)/\1/g") line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/402e0db2_617b2736 PS3, Line 15: AMDFW_ADDRESS=0x$(eval printf %x $(eval expr 4294967295 + 1 - $(($ROMSIZE)) + $CBFS_ADDRESS + $AMDFW_OFFSET + 64)) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/c6d5b3f6_9f797dda PS3, Line 72: --instance 0 --apcb BiosDirL20_Typex60.bin --instance 10 --apcb BiosDirL20_Typex68.bin --apob-base 0x2001000 --bios-bin $BIOS_BIN_FILE --bios-bin-dest $BIOS_BIN_DEST --bios-uncomp-size $BIOS_BIN_SIZE --soft-fuse $SOFT_FUSE --use-pspsecureos --load-s0i3 --combo-capable "--token-unlock" --spi-read-mode 2 --spi-speed 0 --spi-micron-flag 0 --config "fw.cfg" --soc-name "Cezanne" --flashsize $ROMSIZE \ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/12758b42_c8fe135f PS3, Line 84: $CBFSTOOL $IMAGE_NEW add -f amdfw_n.rom -n apu/amdfw -t raw -r COREBOOT -b $(($AMDFW_ADDRESS)) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Gerrit-Change-Number: 55160 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 04 Jun 2021 03:15:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add a function to extract firmwares
by build bot (Jenkins) (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54901 ) Change subject: amdfwtool: Add a function to extract firmwares ...................................................................... Patch Set 13: (1 comment) File util/amdfwtool/extract.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120676): https://review.coreboot.org/c/coreboot/+/54901/comment/437e4536_a2110a38 PS13, Line 91: close (mod_fd); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/54901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a6c7ff56cc11530695d1068763ecdd86282a17 Gerrit-Change-Number: 54901 Gerrit-PatchSet: 13 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:10:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Initialize SPM
by Yu-Ping Wu (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55154 ) Change subject: mb/google/cherry: Initialize SPM ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071 Gerrit-Change-Number: 55154 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 02:53:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cbfstool: Print out the CBFS offset and size
by Bao Zheng (Code Review) June 3, 2021

June 3, 2021

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55158 ) Change subject: cbfstool: Print out the CBFS offset and size ...................................................................... Abandoned cbfstool layout can do this. -- To view, visit https://review.coreboot.org/c/coreboot/+/55158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb7f55180cecfcb7526cf5ae94741b6ae526b66 Gerrit-Change-Number: 55158 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP]amdfwtool: Add a script to replace AMD firmware
by Bao Zheng (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55160 to look at the new patch set (#3). Change subject: [WIP]amdfwtool: Add a script to replace AMD firmware ...................................................................... [WIP]amdfwtool: Add a script to replace AMD firmware Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- A util/amdfwtool/replace.sh 1 file changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/55160/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Gerrit-Change-Number: 55160 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Initialize SPM
by Rex-BC Chen (Code Review) June 3, 2021

June 3, 2021

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, DAWEI CHIEN. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55154 ) Change subject: mb/google/cherry: Initialize SPM ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55154/comment/3d52ef70_1a209b2c PS5, Line 9: This patch adds support for SPM. This adds 43ms > Please put as many words as possible (<= 72 chars). […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071 Gerrit-Change-Number: 55154 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 02:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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