June 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
by Werner Zeh (Code Review) June 4, 2021

June 4, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55034 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 111 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index fa82a68..be2b6c9 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -27,10 +27,27 @@ # Enable DDC for DDI ports C register "DdiPortCDdc" = "1" + # USB related UPDs + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" - # Enable All Root Ports (1-7) + # PCIe root ports related UPDs register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 6b36792..ebe14d5 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -80,8 +80,8 @@ uint8_t RMT; /* USB related */ - struct usb2_port_config usb2_ports[16]; - struct usb3_port_config usb3_ports[10]; + struct usb2_port_config usb2_ports[10]; + struct usb3_port_config usb3_ports[4]; /* Wake Enable Bitmap for USB2 ports */ uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ @@ -103,16 +103,29 @@ /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; + /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; +/* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ + uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; + + /* Probe CLKREQ# signal before enabling CLKREQ# based power management. + * Enable - Default (0) / Disable (1) */ + uint8_t PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS]; + /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS]; + + /* PCIe LTR: Enable - Default (0) / Disable (1) */ + uint8_t PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 88e7d06..98c939f 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,6 +15,25 @@ #include <soc/soc_chip.h> #include <string.h> +/* + * Chip config parameter PcieRpL1Substates uses (UPD value + 1) + * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. + * In order to ensure that mainboard setting does not disable L1 substates + * incorrectly, chip config parameter values are offset by 1 with 0 meaning + * use FSP UPD default. get_l1_substate_control() ensures that the right UPD + * value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable L1 substates + * 2: Use L1.1 + * 3: Use L1.2 (FSP UPD default) + */ +static int get_l1_substate_control(enum L1_substates_control ctl) +{ + if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) + ctl = L1_SS_L1_2; + return ctl - 1; +} + static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -99,6 +118,7 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { + unsigned int i; struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; struct soc_intel_elkhartlake_config *config = config_of_soc(); @@ -154,6 +174,63 @@ /* HECI */ params->Heci3Enabled = config->Heci3Enable; + /* USB configuration */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = config->usb2_ports[i].enable; + params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; + params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ? + config->usb2_ports[i].ocpin : 0xff; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ? + config->usb3_ports[i].ocpin : 0xff; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + params->UsbClockGatingEnable = 1; + params->UsbPowerGatingEnable = 1; + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } + + /* PCIe root ports config */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpClkReqDetect[i] = + !config->PcieRpClkReqDetectDisable[i]; + params->PcieRpL1Substates[i] = + get_l1_substate_control(config->PcieRpL1Substates[i]); + params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i]; + params->PcieRpAdvancedErrorReporting[i] = + !config->PcieRpAdvancedErrorReportingDisable[i]; + params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = config->PciePtm[i]; + params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003; + params->PcieRpLtrMaxSnoopLatency[i] = 0x1003; + /* Virtual Channel 1 to Traffic Class mapping */ + params->PcieRpVc1TcMap[i] = 0x60; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Gerrit-Change-Number: 55034 Gerrit-PatchSet: 11 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP]Allow to build romstage sources inside the bootblock
by Keith Hui (Code Review) June 4, 2021

June 4, 2021

Attention is currently required from: Arthur Heymans, Martin Roth, ron minnich, Paul Menzel, Stefan Reinauer, Angel Pons, Patrick Rudolph, Ron Minnich, Felix Held. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55068 ) Change subject: [WIP]Allow to build romstage sources inside the bootblock ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > You also need to build the current patch set, as the files where only added in patch set 2 [1]. > > [1]: https://review.coreboot.org/c/coreboot/+/55067/1..2 That's it! I needed it as well. Done that. Building for asus/p2b-ls without payload yields this result: Separate romstage Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 17408 none cpu_microcode_blob.bin 0x4500 microcode 83968 none fallback/ramstage 0x18d40 stage 52312 LZMA build_info 0x25a00 raw 98 none fallback/dsdt.aml 0x25ac0 raw 5630 none cmos_layout.bin 0x27100 cmos_layout 704 none fallback/postcar 0x27400 stage 10400 none (empty) 0x29d00 null 79204 none bootblock 0x3d280 bootblock 11088 none romstage folded into bootblock Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none cpu_microcode_blob.bin 0x80 microcode 83968 none fallback/ramstage 0x148c0 stage 52312 LZMA build_info 0x21580 raw 98 none fallback/dsdt.aml 0x21640 raw 5630 none cmos_layout.bin 0x22c80 cmos_layout 704 none fallback/postcar 0x22f80 stage 10400 none (empty) 0x25880 null 88804 none bootblock 0x3b380 bootblock 19008 none For a savings of 9600 bytes. Less than the 10-20k claimed, but still significant. I look forward to further activities on the LTO front. Still I would have to leave out microcode to fit the Adaptec SCSI BIOS lifted from vendor firmware to boot from SCSI drives, or attempt to port aic78u2 to seabios (holy F!). I still have to build it with seabios with a ps/2 init patch for boot testing - I do have issues with a real Model M on ps/2 port. -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Add new Elan touchscreen
by Werner Zeh (Code Review) June 4, 2021

June 4, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54868 ) Change subject: mb/google/dedede/var/cret: Add new Elan touchscreen ...................................................................... mb/google/dedede/var/cret: Add new Elan touchscreen Add Elan eKTH7D18 touchscreen into devicetree for cret. BUG=b:180547935, b:187484857 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54868 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/cret/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 2586322..82002e4 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -147,6 +147,24 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "300" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 16 on end + end end # I2C 2 device pci 15.3 off end # I2C 3 device pci 1c.7 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/54868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab87ddfc7b46420439efa3e7e55c88ad4c27155d Gerrit-Change-Number: 54868 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
by Werner Zeh (Code Review) June 4, 2021

June 4, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54960 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 63 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index dde0e9b..fa82a68 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -12,11 +12,21 @@ register "pmc_gpe0_dw1" = "GPP_F" register "pmc_gpe0_dw2" = "GPP_E" + # Enable heci1 communication + register "HeciEnabled" = "1" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "Heci2Enable" = "1" + # Display related UPDs + # Enable HPD for DDI ports C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports C + register "DdiPortCDdc" = "1" + # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" @@ -104,6 +114,10 @@ # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 5c25e95..88e7d06 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,18 +15,6 @@ #include <soc/soc_chip.h> #include <string.h> -/* - * ME End of Post configuration - * 0 - Disable EOP. - * 1 - Send in PEI (Applicable for FSP in API mode) - * 2 - Send in DXE (Not applicable for FSP in API mode) - */ -enum { - EOP_DISABLE, - EOP_PEI, - EOP_DXE, -} EndOfPost; - static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, @@ -111,12 +99,60 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { + struct device *dev; FSP_S_CONFIG *params = &supd->FspsConfig; + struct soc_intel_elkhartlake_config *config = config_of_soc(); /* Parse device tree and fill in FSP UPDs */ parse_devicetree(params); - /* TODO: Update with UPD override as FSP matures */ + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Check if IGD is present and fill Graphics init param accordingly */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); + + /* Display config */ + params->DdiPortAHpd = config->DdiPortAHpd; + params->DdiPortADdc = config->DdiPortADdc; + params->DdiPortCHpd = config->DdiPortCHpd; + params->DdiPortCDdc = config->DdiPortCDdc; + + /* Use coreboot MP PPI services if Kconfig is enabled */ + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosLock = 0; + params->PchLockDownBiosInterface = 0; + params->PchWriteProtectionEnable[0] = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosLock = 1; + params->PchLockDownBiosInterface = 1; + params->PchWriteProtectionEnable[0] = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } + + /* Disable PAVP */ + params->PavpEnable = 0; + + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); + params->Enable8254ClockGatingOnS3 = 1; + + /* PCH Master Gating Control */ + params->PchPostMasterClockGating = 1; + params->PchPostMasterPowerGating = 1; + + /* HECI */ + params->Heci3Enabled = config->Heci3Enable; /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 15 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/storo: Modify I2C times for touchpad
by Werner Zeh (Code Review) June 4, 2021

June 4, 2021

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55109 ) Change subject: mb/google/dedede/var/storo: Modify I2C times for touchpad ...................................................................... mb/google/dedede/var/storo: Modify I2C times for touchpad Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately (380<frequency<400 kHz). Measured touchpad I2C frequency is 394 kHz BUG=b:189740533 BRANCH=dedede TEST=Build bios and make sure frequency meets specification. Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55109 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 40b17df..6336192 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -26,8 +26,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 125, - .fall_time_ns = 19, + .rise_time_ns = 260, + .fall_time_ns = 50, }, .i2c[1] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/55109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0504a5be6fe9237b8b30783c659a761d10561a Gerrit-Change-Number: 55109 Gerrit-PatchSet: 2 Gerrit-Owner: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add PMC ACPI interface
by EricR Lai (Code Review) June 4, 2021

June 4, 2021

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55172 ) Change subject: soc/intel/alderlake: Add PMC ACPI interface ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0 Gerrit-Change-Number: 55172 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:32:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/storo: Update gpio setting
by Tao Xia (Code Review) June 4, 2021

June 4, 2021

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55175 ) Change subject: mb/google/dedede/var/storo: Update gpio setting ...................................................................... mb/google/dedede/var/storo: Update gpio setting Correct GPIO settings as below reason: 1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF. 2. GPP_B7 should configure as WWAN SAR detect ODL, but set to GPI BUG=b:188956448 BRANCH=dedede TEST=The LTE DPR pin can be pulled down normally when someone get close to the P-sensor antenna. Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Idc214fcd9c4631368a71f4d59bb644df739982ab --- M src/mainboard/google/dedede/variants/storo/gpio.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/55175/1 diff --git a/src/mainboard/google/dedede/variants/storo/gpio.c b/src/mainboard/google/dedede/variants/storo/gpio.c index 3d830e7..a73caf5 100644 --- a/src/mainboard/google/dedede/variants/storo/gpio.c +++ b/src/mainboard/google/dedede/variants/storo/gpio.c @@ -8,14 +8,20 @@ /* A10 : WWAN_EN */ PAD_CFG_GPO(GPP_A10, 1, PWROK), - /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ - PAD_CFG_GPI_IRQ_WAKE(GPP_B7, NONE, DEEP, LEVEL, INVERT), + /* B7 : WWAN_SAR_DETECT_R_ODL */ + PAD_CFG_GPO(GPP_B7, 1, DEEP), /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, UP_20K, DEEP), /* D15 : EN_PP3300_CAMERA */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), /* D22 : AP_I2C_SUB_SDA*/ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* D23 : AP_I2C_SUB_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc214fcd9c4631368a71f4d59bb644df739982ab Gerrit-Change-Number: 55175 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]amdfwtool: Add a script to replace AMD firmware
by build bot (Jenkins) (Code Review) June 4, 2021

June 4, 2021

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55160 ) Change subject: [WIP]amdfwtool: Add a script to replace AMD firmware ...................................................................... Patch Set 3: (4 comments) File util/amdfwtool/replace.sh: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/18fc600f_6045565c PS3, Line 12: CBFS_ADDRESS=$(eval $CBFSTOOL $IMAGE layout | grep "^'COREBOOT'" | sed "s/'COREBOOT' (CBFS, size [0-9]\+, offset $[0-9]\+$)/\1/g") line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/402e0db2_617b2736 PS3, Line 15: AMDFW_ADDRESS=0x$(eval printf %x $(eval expr 4294967295 + 1 - $(($ROMSIZE)) + $CBFS_ADDRESS + $AMDFW_OFFSET + 64)) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/c6d5b3f6_9f797dda PS3, Line 72: --instance 0 --apcb BiosDirL20_Typex60.bin --instance 10 --apcb BiosDirL20_Typex68.bin --apob-base 0x2001000 --bios-bin $BIOS_BIN_FILE --bios-bin-dest $BIOS_BIN_DEST --bios-uncomp-size $BIOS_BIN_SIZE --soft-fuse $SOFT_FUSE --use-pspsecureos --load-s0i3 --combo-capable "--token-unlock" --spi-read-mode 2 --spi-speed 0 --spi-micron-flag 0 --config "fw.cfg" --soc-name "Cezanne" --flashsize $ROMSIZE \ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120677): https://review.coreboot.org/c/coreboot/+/55160/comment/12758b42_c8fe135f PS3, Line 84: $CBFSTOOL $IMAGE_NEW add -f amdfw_n.rom -n apu/amdfw -t raw -r COREBOOT -b $(($AMDFW_ADDRESS)) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Gerrit-Change-Number: 55160 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 04 Jun 2021 03:15:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add a function to extract firmwares
by build bot (Jenkins) (Code Review) June 4, 2021

June 4, 2021

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54901 ) Change subject: amdfwtool: Add a function to extract firmwares ...................................................................... Patch Set 13: (1 comment) File util/amdfwtool/extract.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120676): https://review.coreboot.org/c/coreboot/+/54901/comment/437e4536_a2110a38 PS13, Line 91: close (mod_fd); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/54901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a6c7ff56cc11530695d1068763ecdd86282a17 Gerrit-Change-Number: 54901 Gerrit-PatchSet: 13 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 03:10:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Initialize SPM
by Yu-Ping Wu (Code Review) June 4, 2021

June 4, 2021

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55154 ) Change subject: mb/google/cherry: Initialize SPM ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f17f6d51fc9ad2d23c71c3c5cd29fdc777dc071 Gerrit-Change-Number: 55154 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: DAWEI CHIEN <dawei.chien(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 02:53:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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