coreboot-gerrit June 2021

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/bc317dcc_d85b6d3a PS4, Line 7: soc/mediatek/mt8195: fix GPIO register offset Plural: offsets? https://review.coreboot.org/c/coreboot/+/55163/comment/552895e2_4f684b2a PS4, Line 10: Where did you get the new values from? Did something not work before and works now? -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55089 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Gerrit-Change-Number: 55089 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:57:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak, Werner Zeh, Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:55:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Arthur Heymans (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Paul Menzel, Stefan Reinauer, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Patch Set 3: (1 comment) File Documentation/technotes/2021-05-selectable-serial-console.md: https://review.coreboot.org/c/coreboot/+/54385/comment/7b09a841_04874626 PS1, Line 112: and change the default to whatever is found there. > SGTM in general, but you removed the part about forgoing the bootblock now? That part is still important -- remember that non-x86 platforms can't access flash until a lot of other initialization in the bootblock has happened. (Also -- this is just something to keep in mind for the implementation -- you'll need some safeguards to avoid recursion when the CBFS code tries to print things.) Even on x86 this could be important on some setups. For instance with Intel bootguard/CBnT the RO part of the flash is not considered trusted so depending on ro only cbfs access should be avoided. -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:54:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Set RTC century byte offset in FADT x86-wide
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Werner Zeh, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55012 ) Change subject: arch/x86: Set RTC century byte offset in FADT x86-wide ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55012/comment/60f087b4_507ec65b PS2, Line 20: A note, how to test/verify the change (the FADT) would be great, and where you tested it. -- To view, visit https://review.coreboot.org/c/coreboot/+/55012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa5ddc368c129a5f847c64064374aae2d4f0c43 Gerrit-Change-Number: 55012 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:54:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Mario Scheithauer (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Werner Zeh, Kyösti Mälkki. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:35:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
by Mario Scheithauer (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55089 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Gerrit-Change-Number: 55089 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:30:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55169 ) Change subject: mb/lenovo/t410: Enable WLAN and WUSB PCIe ports ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26ace6e043c7c66f8944f0986923014703423b8c Gerrit-Change-Number: 55169 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:27:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t410: Update PCH PCIe RP comments
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55171 ) Change subject: mb/lenovo/t410: Update PCH PCIe RP comments ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c267ff048959b131c22c07695212e8bd90c3f4 Gerrit-Change-Number: 55171 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:26:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset
by Rex-BC Chen (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offset ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/6f65cc49_320e2fa4 PS1, Line 9: Fix GPIO pu/pd offset. > Do you have a reference for these offsets so we can know it's now correct? […] In file MT8195 Register Map_V0.2 -1.pdf (https://drive.google.com/drive/folders/12qTn0CBvrmV1UNyJiWNEJGEpj_OGGfzl?re…) chapter: 3.2 GPIO Controller (page3272) control register name: PUPD_CFG0 PU_CFG0 offset should be fix is which bit control GPIO PUPD/PU Detail: 3.2.2 IOCGF_LM PUPD_CFG0 (page:3347) PU_CFG0 (page:3348) 3.2.3 IOCGF_BL PU_CFG0 (page:3373) 3.2.4 IOCGF_BM PU_CFG0 (page:3400) 3.2.5 IOCGF_BR PUPD_CFG0 (page:3428) PU_CFG0 (page:3432) 3.2.6 IOCGF_RB PUPD_CFG0 (page:3456) 3.2.7 IOCGF_TL PUPD_CFG0 (page:3473) PU_CFG0 (page:3475) -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 05:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2021