coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

1 participants
7127 discussions

Change in coreboot[master]: cpu/x86/lapic: Separate stop_this_cpu()
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55193 ) Change subject: cpu/x86/lapic: Separate stop_this_cpu() ...................................................................... cpu/x86/lapic: Separate stop_this_cpu() Function is needed with PARALLEL_MP and excluding guard will be added to the source file. The incompatibilities with X2APIC_SUPPORT have been fixed so the exclusion is removed here too. Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/lapic_cpu_init.c A src/cpu/x86/lapic/lapic_cpu_stop.c M src/include/cpu/x86/lapic.h 5 files changed, 72 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/55193/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index b05a071..e535eeb 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -29,13 +29,11 @@ prompt "Set X2APIC mode" bool depends on PARALLEL_MP - depends on !AP_IN_SIPI_WAIT config X2APIC_RUNTIME prompt "Support both XAPIC and X2APIC" bool depends on PARALLEL_MP - depends on !AP_IN_SIPI_WAIT endchoice diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index ea16014..c0adcfc 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c +ramstage-$(CONFIG_AP_IN_SIPI_WAIT) += lapic_cpu_stop.c ramstage-$(CONFIG_SMP) += secondary.S bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index d8cad23..3a164a6 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -6,7 +6,6 @@ #include <cpu/x86/smi_deprecated.h> #include <acpi/acpi.h> #include <delay.h> -#include <halt.h> #include <lib.h> #include <string.h> #include <symbols.h> @@ -283,73 +282,6 @@ return result; } -#if CONFIG(AP_IN_SIPI_WAIT) - -/** - * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of - * delay. - * An undefined number of instruction cycles will complete. All global locks - * must be released before INIT IPI and no printk is allowed after this. - * De-asserting INIT IPI is a no-op on later Intel CPUs. - * - * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled - * but running thread may halt without releasing the lock and effectively - * deadlock other CPUs. - */ -#define DEBUG_HALT_SELF 0 - -#if DEBUG_HALT_SELF -#define dprintk(LEVEL, args...) do { printk(LEVEL, ##args); } while (0) -#else -#define dprintk(LEVEL, args...) do { } while (0) -#endif - -static void wait_for_ipi_completion_without_printk(const int timeout_ms) -{ - int loops = timeout_ms * 10; - uint32_t send_status; - - /* wait for the ipi send to finish */ - dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); - do { - dprintk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_busy(); - } while (send_status && (--loops > 0)); - - if (send_status) - dprintk(BIOS_ERR, "timed out\n"); -} - -/** - * Normally this function is defined in lapic.h as an always inline function - * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. - * I think all hyperthreading CPUs might need this version, but I could only - * verify this on the Intel Core Duo - */ -void stop_this_cpu(void) -{ - const int timeout_100ms = 100; - unsigned long id = lapicid(); - - printk(BIOS_DEBUG, "CPU %ld going down...\n", id); - - /* send an LAPIC INIT to myself */ - lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, id); - wait_for_ipi_completion_without_printk(timeout_100ms); - - mdelay(10); - - dprintk(BIOS_SPEW, "Deasserting INIT.\n"); - - /* Deassert the LAPIC INIT */ - lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, id); - wait_for_ipi_completion_without_printk(timeout_100ms); - - halt(); -} -#endif - /* C entry point of secondary cpus */ asmlinkage void secondary_cpu_init(unsigned int index) { diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c new file mode 100644 index 0000000..e933ce4 --- /dev/null +++ b/src/cpu/x86/lapic/lapic_cpu_stop.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <delay.h> +#include <halt.h> + +/** + * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of + * delay. + * An undefined number of instruction cycles will complete. All global locks + * must be released before INIT IPI and no printk is allowed after this. + * De-asserting INIT IPI is a no-op on later Intel CPUs. + * + * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled + * but running thread may halt without releasing the lock and effectively + * deadlock other CPUs. + */ +#define DEBUG_HALT_SELF 0 + +#if DEBUG_HALT_SELF +#define dprintk(LEVEL, args...) do { printk(LEVEL, ##args); } while (0) +#else +#define dprintk(LEVEL, args...) do { } while (0) +#endif + +static void wait_for_ipi_completion_without_printk(const int timeout_ms) +{ + int loops = timeout_ms * 10; + uint32_t send_status; + + /* wait for the ipi send to finish */ + dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); + do { + dprintk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_busy(); + } while (send_status && (--loops > 0)); + + if (send_status) + dprintk(BIOS_ERR, "timed out\n"); +} + +/** + * Normally this function is defined in lapic.h as an always inline function + * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. + * I think all hyperthreading CPUs might need this version, but I could only + * verify this on the Intel Core Duo + */ +void stop_this_cpu(void) +{ + const int timeout_100ms = 100; + unsigned long id = lapicid(); + + printk(BIOS_DEBUG, "CPU %ld going down...\n", id); + + /* send an LAPIC INIT to myself */ + lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, id); + wait_for_ipi_completion_without_printk(timeout_100ms); + + mdelay(10); + + dprintk(BIOS_SPEW, "Deasserting INIT.\n"); + + /* Deassert the LAPIC INIT */ + lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, id); + wait_for_ipi_completion_without_printk(timeout_100ms); + + halt(); +} diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 13510ea..b6d4330 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -184,7 +184,7 @@ #if !CONFIG(AP_IN_SIPI_WAIT) /* If we need to go back to sipi wait, we use the long non-inlined version of - * this function in lapic_cpu_init.c + * this function in lapic_cpu_stop.c */ static __always_inline void stop_this_cpu(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/55193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Gerrit-Change-Number: 55193 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Add wait_ipi_completion() helpers
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55192 ) Change subject: cpu/x86/lapic: Add wait_ipi_completion() helpers ...................................................................... cpu/x86/lapic: Add wait_ipi_completion() helpers Change-Id: Ib9c404cb55b96dcc5639287c214c5c8f468c0529 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c 1 file changed, 42 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/55192/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 132cb5a..d8cad23 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -88,9 +88,25 @@ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); } +static uint32_t wait_for_ipi_completion(const int timeout_ms) +{ + int loops = timeout_ms * 10; + uint32_t send_status; + + /* wait for the ipi send to finish */ + printk(BIOS_SPEW, "Waiting for send to finish...\n"); + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_busy(); + } while (send_status && (--loops > 0)); + + return send_status; +} + static int lapic_start_cpu(unsigned long apicid) { - int timeout; + const int timeout_100ms = 100; uint32_t send_status, accept_status; int j, maxlvt; @@ -105,14 +121,8 @@ */ lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, apicid); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_busy(); - } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { + send_status = wait_for_ipi_completion(timeout_100ms); + if (send_status) { printk(BIOS_ERR, "CPU %ld: First APIC write timed out. " "Disabling\n", apicid); // too bad. @@ -131,14 +141,8 @@ lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, apicid); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_busy(); - } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { + send_status = wait_for_ipi_completion(timeout_100ms); + if (send_status) { printk(BIOS_ERR, "CPU %ld: Second APIC write timed out. " "Disabling\n", apicid); // too bad. @@ -172,13 +176,7 @@ printk(BIOS_SPEW, "Startup point 1.\n"); - printk(BIOS_SPEW, "Waiting for send to finish...\n"); - timeout = 0; - do { - printk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_busy(); - } while (send_status && (timeout++ < 1000)); + send_status = wait_for_ipi_completion(timeout_100ms); /* * Give the other CPU some time to accept the IPI. @@ -306,6 +304,23 @@ #define dprintk(LEVEL, args...) do { } while (0) #endif +static void wait_for_ipi_completion_without_printk(const int timeout_ms) +{ + int loops = timeout_ms * 10; + uint32_t send_status; + + /* wait for the ipi send to finish */ + dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); + do { + dprintk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_busy(); + } while (send_status && (--loops > 0)); + + if (send_status) + dprintk(BIOS_ERR, "timed out\n"); +} + /** * Normally this function is defined in lapic.h as an always inline function * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. @@ -314,27 +329,14 @@ */ void stop_this_cpu(void) { - int timeout; - unsigned long send_status; + const int timeout_100ms = 100; unsigned long id = lapicid(); printk(BIOS_DEBUG, "CPU %ld going down...\n", id); /* send an LAPIC INIT to myself */ lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, id); - - /* wait for the ipi send to finish */ - dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); - - timeout = 0; - do { - dprintk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_busy(); - } while (send_status && (timeout++ < 1000)); - - if (timeout >= 1000) - dprintk(BIOS_ERR, "timed out\n"); + wait_for_ipi_completion_without_printk(timeout_100ms); mdelay(10); @@ -342,18 +344,7 @@ /* Deassert the LAPIC INIT */ lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, id); - - dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); - - timeout = 0; - do { - dprintk(BIOS_SPEW, "+"); - udelay(100); - send_status = lapic_busy(); - } while (send_status && (timeout++ < 1000)); - - if (timeout >= 1000) - dprintk(BIOS_ERR, "timed out\n"); + wait_for_ipi_completion_without_printk(timeout_100ms); halt(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9c404cb55b96dcc5639287c214c5c8f468c0529 Gerrit-Change-Number: 55192 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Add lapic_busy() helper
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55191 to review the following change. Change subject: cpu/x86/lapic: Add lapic_busy() helper ...................................................................... cpu/x86/lapic: Add lapic_busy() helper Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h 3 files changed, 20 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/55191/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 5988919..132cb5a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -110,7 +110,7 @@ do { printk(BIOS_SPEW, "+"); udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + send_status = lapic_busy(); } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { printk(BIOS_ERR, "CPU %ld: First APIC write timed out. " @@ -136,7 +136,7 @@ do { printk(BIOS_SPEW, "+"); udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + send_status = lapic_busy(); } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { printk(BIOS_ERR, "CPU %ld: Second APIC write timed out. " @@ -177,7 +177,7 @@ do { printk(BIOS_SPEW, "+"); udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + send_status = lapic_busy(); } while (send_status && (timeout++ < 1000)); /* @@ -330,7 +330,7 @@ do { dprintk(BIOS_SPEW, "+"); udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + send_status = lapic_busy(); } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) @@ -349,7 +349,7 @@ do { dprintk(BIOS_SPEW, "+"); udelay(100); - send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + send_status = lapic_busy(); } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 87ddb0d..ad45ee9 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -403,7 +403,7 @@ int total = 0; int timeout = 0; - while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) { + while (lapic_busy()) { udelay(delay_step); total += delay_step; if (total >= total_delay) { @@ -457,7 +457,7 @@ return 0; } - if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_ERR, "timed out. Aborting.\n"); @@ -472,7 +472,7 @@ mdelay(10); /* Send 1st SIPI */ - if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_ERR, "timed out. Aborting.\n"); @@ -497,7 +497,7 @@ return 0; /* Send 2nd SIPI */ - if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_ERR, "timed out. Aborting.\n"); @@ -676,7 +676,7 @@ return; } - if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { + if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { printk(BIOS_DEBUG, "timed out. Aborting.\n"); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e297e3b7..13510ea 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -35,6 +35,11 @@ xapic_write_atomic(LAPIC_ICR, icrlow); } +static __always_inline int xapic_busy(void) +{ + return xapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; +} + #define lapic_read_around(x) lapic_read(x) #define lapic_write_around(x, y) xapic_write_atomic((x), (y)) @@ -124,9 +129,12 @@ xapic_send_ipi(icrlow, apicid); } -static __always_inline void lapic_wait_icr_idle(void) +static __always_inline int lapic_busy(void) { - do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); + if (is_x2apic_mode()) + return 0; + else + return xapic_busy(); } static inline void enable_lapic(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/55191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261 Gerrit-Change-Number: 55191 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Add lapic_send_ipi() helper
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55190 to review the following change. Change subject: cpu/x86/lapic: Add lapic_send_ipi() helper ...................................................................... cpu/x86/lapic: Add lapic_send_ipi() helper Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h 3 files changed, 26 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/55190/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f73c4b2..5988919 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -103,14 +103,7 @@ /* * Turn INIT on target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* - * Send IPI - */ - - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT - | LAPIC_DM_INIT); + lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, apicid); printk(BIOS_SPEW, "Waiting for send to finish...\n"); timeout = 0; @@ -136,11 +129,7 @@ printk(BIOS_SPEW, "Deasserting INIT.\n"); - /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* Send IPI */ - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, apicid); printk(BIOS_SPEW, "Waiting for send to finish...\n"); timeout = 0; @@ -174,13 +163,7 @@ * STARTUP IPI */ - /* Target chip */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - - /* Boot on the stack */ - /* Kick the second */ - lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP - | (AP_SIPI_VECTOR >> 12)); + lapic_send_ipi(LAPIC_DM_STARTUP | (AP_SIPI_VECTOR >> 12), apicid); /* * Give the other CPU some time to accept the IPI. @@ -333,16 +316,12 @@ { int timeout; unsigned long send_status; - unsigned long id; - - id = lapicid(); + unsigned long id = lapicid(); printk(BIOS_DEBUG, "CPU %ld going down...\n", id); /* send an LAPIC INIT to myself */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | - LAPIC_INT_ASSERT | LAPIC_DM_INIT); + lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT, id); /* wait for the ipi send to finish */ dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); @@ -362,8 +341,7 @@ dprintk(BIOS_SPEW, "Deasserting INIT.\n"); /* Deassert the LAPIC INIT */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); - lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + lapic_send_ipi(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT, id); dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 893e8f1..87ddb0d 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -467,9 +467,7 @@ } /* Send INIT IPI to all but self. */ - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); - lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_INIT); + lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0); printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10); @@ -483,9 +481,8 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); - lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_STARTUP | sipi_vector); + lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, + 0); printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_ERR, "timed out.\n"); @@ -509,9 +506,8 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); - lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_STARTUP | sipi_vector); + lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector, + 0); printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_ERR, "timed out.\n"); @@ -689,8 +685,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid())); - lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_SMI); + lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); else diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 7eba327..e297e3b7 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -29,10 +29,15 @@ : : "memory", "cc"); } +static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) +{ + xapic_write_atomic(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + xapic_write_atomic(LAPIC_ICR, icrlow); +} + #define lapic_read_around(x) lapic_read(x) #define lapic_write_around(x, y) xapic_write_atomic((x), (y)) - static __always_inline uint32_t x2apic_read(unsigned int reg) { uint32_t value, index; @@ -111,6 +116,14 @@ } } +static __always_inline void lapic_send_ipi(uint32_t icrlow, uint32_t apicid) +{ + if (is_x2apic_mode()) + x2apic_send_ipi(icrlow, apicid); + else + xapic_send_ipi(icrlow, apicid); +} + static __always_inline void lapic_wait_icr_idle(void) { do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); -- To view, visit https://review.coreboot.org/c/coreboot/+/55190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e Gerrit-Change-Number: 55190 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Redo DEBUG_HALT_SELF
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55189 ) Change subject: cpu/x86/lapic: Redo DEBUG_HALT_SELF ...................................................................... cpu/x86/lapic: Redo DEBUG_HALT_SELF Change-Id: I7e42519d5bcee95970d366fd64923de874098172 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c 1 file changed, 21 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/55189/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 31743c7..f73c4b2 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -317,6 +317,12 @@ */ #define DEBUG_HALT_SELF 0 +#if DEBUG_HALT_SELF +#define dprintk(LEVEL, args...) do { printk(LEVEL, ##args); } while (0) +#else +#define dprintk(LEVEL, args...) do { } while (0) +#endif + /** * Normally this function is defined in lapic.h as an always inline function * that just keeps the CPU in a hlt() loop. This does not work on all CPUs. @@ -339,47 +345,37 @@ LAPIC_INT_ASSERT | LAPIC_DM_INIT); /* wait for the ipi send to finish */ -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Waiting for send to finish...\n"); -#endif + dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); + timeout = 0; do { -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "+"); -#endif + dprintk(BIOS_SPEW, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { -#if DEBUG_HALT_SELF - printk(BIOS_ERR, "timed out\n"); -#endif - } + + if (timeout >= 1000) + dprintk(BIOS_ERR, "timed out\n"); + mdelay(10); -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Deasserting INIT.\n"); -#endif + dprintk(BIOS_SPEW, "Deasserting INIT.\n"); + /* Deassert the LAPIC INIT */ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "Waiting for send to finish...\n"); -#endif + dprintk(BIOS_SPEW, "Waiting for send to finish...\n"); + timeout = 0; do { -#if DEBUG_HALT_SELF - printk(BIOS_SPEW, "+"); -#endif + dprintk(BIOS_SPEW, "+"); udelay(100); send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); - if (timeout >= 1000) { -#if DEBUG_HALT_SELF - printk(BIOS_ERR, "timed out\n"); -#endif - } + + if (timeout >= 1000) + dprintk(BIOS_ERR, "timed out\n"); halt(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e42519d5bcee95970d366fd64923de874098172 Gerrit-Change-Number: 55189 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Declare start_cpu() static
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55188 ) Change subject: cpu/x86/lapic: Declare start_cpu() static ...................................................................... cpu/x86/lapic: Declare start_cpu() static This is for the !PARALLEL_MP paths. Change-Id: If4b91834a1b6de2a902ab914610ab76c1423f1e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/55188/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f89d9e3..31743c7 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -241,7 +241,7 @@ volatile unsigned long secondary_stack; volatile unsigned int secondary_cpu_index; -int start_cpu(struct device *cpu) +static int start_cpu(struct device *cpu) { struct cpu_info *info; uintptr_t stack_top; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index bb62077..7eba327 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -190,7 +190,4 @@ disable_lapic(); } -struct device; -int start_cpu(struct device *cpu); - #endif /* CPU_X86_LAPIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4b91834a1b6de2a902ab914610ab76c1423f1e9 Gerrit-Change-Number: 55188 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Add lapic_update32() helper
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55187 ) Change subject: cpu/x86/lapic: Add lapic_update32() helper ...................................................................... cpu/x86/lapic: Add lapic_update32() helper Change-Id: I57c5d85d3098f9d59f26f427fe16829e4e769194 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 2 files changed, 32 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/55187/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 09dd003..468a5dc 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -2,10 +2,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> - -#if !CONFIG(XAPIC_ONLY) -#error "BUG: lapic_write_around() needs to be fixed for X2APIC." -#endif +#include <stdint.h> void lapic_virtual_wire_mode_init(void) { @@ -25,31 +22,20 @@ /* * Set Task Priority to 'accept all'. */ - lapic_write_around(LAPIC_TASKPRI, - lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); + lapic_update32(LAPIC_TASKPRI, ~LAPIC_TPRI_MASK, 0); /* Put the local APIC in virtual wire mode */ - lapic_write_around(LAPIC_SPIV, - (lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK)) - | LAPIC_SPIV_ENABLE); - lapic_write_around(LAPIC_LVT0, - (lapic_read_around(LAPIC_LVT0) & - ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | - LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | - LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | - LAPIC_DELIVERY_MODE_MASK)) - | (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | - LAPIC_DELIVERY_MODE_EXTINT) - ); - lapic_write_around(LAPIC_LVT1, - (lapic_read_around(LAPIC_LVT1) & - ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | - LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY | - LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | - LAPIC_DELIVERY_MODE_MASK)) - | (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | - LAPIC_DELIVERY_MODE_NMI) - ); + lapic_update32(LAPIC_SPIV, ~LAPIC_VECTOR_MASK, LAPIC_SPIV_ENABLE); + + uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_LVT_REMOTE_IRR | + LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 | + LAPIC_DELIVERY_MODE_MASK; + + lapic_update32(LAPIC_LVT0, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_EXTINT); + + lapic_update32(LAPIC_LVT1, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING | + LAPIC_DELIVERY_MODE_NMI); printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid()); printk(BIOS_INFO, "done.\n"); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index c23680b..bb62077 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -92,6 +92,25 @@ xapic_write(reg, v); } +static __always_inline void lapic_update32(unsigned int reg, uint32_t mask, uint32_t or) +{ + if (is_x2apic_mode()) { + uint32_t index; + msr_t msr; + index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4); + msr = rdmsr(index); + msr.lo &= mask; + msr.lo |= or; + wrmsr(index, msr); + } else { + uint32_t value; + value = xapic_read(reg); + value &= mask; + value |= or; + xapic_write_atomic(reg, value); + } +} + static __always_inline void lapic_wait_icr_idle(void) { do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); -- To view, visit https://review.coreboot.org/c/coreboot/+/55187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57c5d85d3098f9d59f26f427fe16829e4e769194 Gerrit-Change-Number: 55187 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/x86/lapic: Regroup LAPIC accessors
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55186 ) Change subject: cpu/x86/lapic: Regroup LAPIC accessors ...................................................................... cpu/x86/lapic: Regroup LAPIC accessors Change-Id: I4347fc6542f59f56bd8400181efa30247794cf96 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/x86/lapic.h 1 file changed, 63 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/55186/1 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 4c57847..c23680b 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -8,6 +8,61 @@ #include <halt.h> #include <stdint.h> +static __always_inline uint32_t xapic_read(unsigned int reg) +{ + return read32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg)); +} + +static __always_inline void xapic_write(unsigned int reg, uint32_t v) +{ + write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); +} + +static inline void xapic_write_atomic(unsigned long reg, uint32_t v) +{ + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg); + + asm volatile ("xchgl %0, %1\n" + : "+r" (v), "+m" (*(ptr)) + : : "memory", "cc"); +} + +#define lapic_read_around(x) lapic_read(x) +#define lapic_write_around(x, y) xapic_write_atomic((x), (y)) + + +static __always_inline uint32_t x2apic_read(unsigned int reg) +{ + uint32_t value, index; + msr_t msr; + + index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4); + msr = rdmsr(index); + value = msr.lo; + return value; +} + +static __always_inline void x2apic_write(unsigned int reg, uint32_t v) +{ + uint32_t index; + msr_t msr; + + index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4); + msr.hi = 0x0; + msr.lo = v; + wrmsr(index, msr); +} + +static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) +{ + msr_t icr; + icr.hi = apicid; + icr.lo = icrlow; + wrmsr(X2APIC_MSR_ICR_ADDRESS, icr); +} + static inline bool is_x2apic_mode(void) { if (CONFIG(XAPIC_ONLY)) @@ -21,41 +76,20 @@ return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED); } -static inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) -{ - msr_t icr; - icr.hi = apicid; - icr.lo = icrlow; - wrmsr(X2APIC_MSR_ICR_ADDRESS, icr); -} - static __always_inline uint32_t lapic_read(unsigned int reg) { - uint32_t value, index; - msr_t msr; - - if (is_x2apic_mode()) { - index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4); - msr = rdmsr(index); - value = msr.lo; - } else { - value = read32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg)); - } - return value; + if (is_x2apic_mode()) + return x2apic_read(reg); + else + return xapic_read(reg); } static __always_inline void lapic_write(unsigned int reg, uint32_t v) { - msr_t msr; - uint32_t index; - if (is_x2apic_mode()) { - index = X2APIC_MSR_BASE_ADDRESS + (uint32_t)(reg >> 4); - msr.hi = 0x0; - msr.lo = v; - wrmsr(index, msr); - } else { - write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); - } + if (is_x2apic_mode()) + x2apic_write(reg, v); + else + xapic_write(reg, v); } static __always_inline void lapic_wait_icr_idle(void) @@ -121,20 +155,6 @@ void stop_this_cpu(void); #endif -static inline void lapic_write_atomic(unsigned long reg, uint32_t v) -{ - volatile uint32_t *ptr; - - ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg); - - asm volatile ("xchgl %0, %1\n" - : "+r" (v), "+m" (*(ptr)) - : : "memory", "cc"); -} - -# define lapic_read_around(x) lapic_read(x) -# define lapic_write_around(x, y) lapic_write_atomic((x), (y)) - void lapic_virtual_wire_mode_init(void); /* See if I need to initialize the local APIC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4347fc6542f59f56bd8400181efa30247794cf96 Gerrit-Change-Number: 55186 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/generic/ioapic: Use arch/x86/ioapic
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55185 ) Change subject: drivers/generic/ioapic: Use arch/x86/ioapic ...................................................................... drivers/generic/ioapic: Use arch/x86/ioapic Change-Id: Ibfaf6693288005463e45831fe100a5052e97cf2f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/drivers/generic/ioapic/ioapic.c 3 files changed, 20 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/55185/1 diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 33f1524..ebdbe8c 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -31,6 +31,9 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id); void setup_ioapic(void *ioapic_base, u8 ioapic_id); void clear_ioapic(void *ioapic_base); + +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, + bool enable_virtual_wire); #endif #endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 3b814ad..f463505 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -109,11 +109,14 @@ } -static void load_vectors(void *ioapic_base) +void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool irq_on_fsb, + bool enable_virtual_wire) { - int first = 1, last; + int first = 0, last; - if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) { + set_ioapic_id(ioapic_base, ioapic_id); + + if (irq_on_fsb) { /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -121,20 +124,24 @@ printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); - } else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) { + } else { printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); } - - route_i8259_irq0(ioapic_base); + + if (enable_virtual_wire) { + route_i8259_irq0(ioapic_base); + first = 1; + } last = ioapic_interrupt_count(ioapic_base) - 1; clear_vectors(ioapic_base, first, last); } + void setup_ioapic(void *ioapic_base, u8 ioapic_id) { - set_ioapic_id(ioapic_base, ioapic_id); - load_vectors(ioapic_base); + setup_ioapic_helper(ioapic_base, ioapic_id, + CONFIG(IOAPIC_INTERRUPTS_ON_FSB), true); } diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index e33d584..708d9a1 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -9,76 +9,12 @@ static void ioapic_init(struct device *dev) { struct drivers_generic_ioapic_config *config = dev->chip_info; - u32 bsp_lapicid = lapicid(); - u32 low, high; - u32 i, ioapic_interrupts; - void *ioapic_base; - u8 ioapic_id; if (!dev->enabled || !config) return; - ioapic_base = config->base; - ioapic_id = config->apicid; - - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", - ioapic_base); - printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); - - if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); - /* Set IOAPIC ID if it has been specified. */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | - (ioapic_id << 24)); - } - - /* Read the available number of interrupts. */ - ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; - if (!ioapic_interrupts || ioapic_interrupts == 0xff) - ioapic_interrupts = 24; - printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); - - if (config->irq_on_fsb) { - /* - * For the Pentium 4 and above APICs deliver their interrupts - * on the front side bus, enable that. - */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); - io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); - } else { - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); - io_apic_write(ioapic_base, 0x03, 0); - } - - if (config->enable_virtual_wire) { - /* Enable Virtual Wire Mode. */ - low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; - high = bsp_lapicid << (56 - 32); - - io_apic_write(ioapic_base, 0x10, low); - io_apic_write(ioapic_base, 0x11, high); - - if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { - printk(BIOS_WARNING, "IOAPIC not responding.\n"); - return; - } - - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, - high, low); - } - low = INT_DISABLED; - high = NONE; - - for (i = 1; i < ioapic_interrupts; i++) { - io_apic_write(ioapic_base, i * 2 + 0x10, low); - io_apic_write(ioapic_base, i * 2 + 0x11, high); - - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); - } + setup_ioapic_helper(config->base, config->apicid, config->irq_on_fsb, + config->enable_virtual_wire); } static void ioapic_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/55185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfaf6693288005463e45831fe100a5052e97cf2f Gerrit-Change-Number: 55185 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/ioapic: Add write_vector() helper
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55184 ) Change subject: arch/x86/ioapic: Add write_vector() helper ...................................................................... arch/x86/ioapic: Add write_vector() helper Change-Id: I4a44aada7d3dbc016e4044c351534a0d8520f0b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/ioapic.c 1 file changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/55184/1 diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 1a8b489..3b814ad 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -18,6 +18,15 @@ write32(ioapic_base + 0x10, value); } +static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low) +{ + io_apic_write(ioapic_base, vector * 2 + 0x10, low); + io_apic_write(ioapic_base, vector * 2 + 0x11, high); + + printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n", + vector, high, low); +} + static int ioapic_interrupt_count(void *ioapic_base) { /* Read the available number of interrupts. */ @@ -42,13 +51,8 @@ low = INT_DISABLED; high = NONE; - for (i = first; i <= last; i++) { - io_apic_write(ioapic_base, i * 2 + 0x10, low); - io_apic_write(ioapic_base, i * 2 + 0x11, high); - - printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n", - i, high, low); - } + for (i = first; i <= last; i++) + write_vector(ioapic_base, i, high, low); if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { printk(BIOS_WARNING, "IOAPIC not responding.\n"); @@ -75,15 +79,12 @@ low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); - io_apic_write(ioapic_base, 0x10, low); - io_apic_write(ioapic_base, 0x11, high); + write_vector(ioapic_base, 0, high, low); if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { printk(BIOS_WARNING, "IOAPIC not responding.\n"); return; } - - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); } void set_ioapic_id(void *ioapic_base, u8 ioapic_id) -- To view, visit https://review.coreboot.org/c/coreboot/+/55184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a44aada7d3dbc016e4044c351534a0d8520f0b2 Gerrit-Change-Number: 55184 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2021