coreboot-gerrit June 2021

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Change in coreboot[master]: cpu/x86: Drop Kconfig PARALLEL_CPU_INIT
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55203 ) Change subject: cpu/x86: Drop Kconfig PARALLEL_CPU_INIT ...................................................................... cpu/x86: Drop Kconfig PARALLEL_CPU_INIT Change-Id: Ibe2c24228045cbf1ed2a6b0cb0a67848cbf03019 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic_cpu_init.c 3 files changed, 9 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55203/1 diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 38f6efc..93d29d4 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -6,9 +6,7 @@ #include <option.h> #include <smp/spinlock.h> -#if CONFIG(PARALLEL_CPU_INIT) -#error Intel hyper-threading requires serialized CPU init -#endif +/* Intel hyper-threading requires serialized CPU init. */ static int first_time = 1; static int disable_siblings = !CONFIG(LOGICAL_CPUS); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index c769865..de5535f 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,8 +1,3 @@ -# TODO These two options look too similar -config PARALLEL_CPU_INIT - bool - default n - config PARALLEL_MP def_bool y depends on !LEGACY_CPU_INIT diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index fe1c824..1c1c15d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -20,6 +20,8 @@ #include <stdlib.h> #include <thread.h> +const int parallel_cpu_init = false; + /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -287,7 +289,7 @@ { atomic_inc(&active_cpus); - if (!CONFIG(PARALLEL_CPU_INIT)) + if (!parallel_cpu_init) spin_lock(&start_cpu_lock); #ifdef __SSE3__ @@ -302,7 +304,7 @@ #endif cpu_initialize(index); - if (!CONFIG(PARALLEL_CPU_INIT)) + if (!parallel_cpu_init) spin_unlock(&start_cpu_lock); atomic_dec(&active_cpus); @@ -319,7 +321,7 @@ if (cpu->path.type != DEVICE_PATH_APIC) continue; - if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu)) + if (parallel_cpu_init && (cpu == bsp_cpu)) continue; if (!cpu->enabled) @@ -333,7 +335,7 @@ printk(BIOS_ERR, "CPU 0x%02x would not start!\n", cpu->path.apic.apic_id); - if (!CONFIG(PARALLEL_CPU_INIT)) + if (!parallel_cpu_init) udelay(10); } @@ -438,13 +440,13 @@ smm_init(); /* start all aps at first, so we can init ECC all together */ - if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT)) + if (is_smp_boot() && parallel_cpu_init) start_other_cpus(cpu_bus, info->cpu); /* Initialize the bootstrap processor */ cpu_initialize(0); - if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT)) + if (is_smp_boot() && !parallel_cpu_init) start_other_cpus(cpu_bus, info->cpu); /* Now wait the rest of the cpus stop*/ -- To view, visit https://review.coreboot.org/c/coreboot/+/55203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe2c24228045cbf1ed2a6b0cb0a67848cbf03019 Gerrit-Change-Number: 55203 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_2065x: Drop select PARALLEL_CPU_INIT
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55202 ) Change subject: cpu/intel/model_2065x: Drop select PARALLEL_CPU_INIT ...................................................................... cpu/intel/model_2065x: Drop select PARALLEL_CPU_INIT It's not evaluated on PARALLEL_MP path. Change-Id: I67d9f40daa4e92301d76927f73be93cb768c45d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_2065x/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/55202/1 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 31105ec..e4714f5 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -11,7 +11,6 @@ select UDELAY_TSC select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS - select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/55202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67d9f40daa4e92301d76927f73be93cb768c45d5 Gerrit-Change-Number: 55202 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/hyperthreading: Build only for selected models
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55201 ) Change subject: cpu/intel/hyperthreading: Build only for selected models ...................................................................... cpu/intel/hyperthreading: Build only for selected models Implements intel_sibling_init() that is mostly superseded. Change-Id: I4956493d8c0c6b922343e060d2d2bd0ec20f5bb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_m/Makefile.inc M src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/intel/socket_p/Makefile.inc 9 files changed, 4 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/55201/1 diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index 5d60d21..fa1b51a 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1,4 +1,5 @@ subdirs-y += ../common +subdirs-y += ../hyperthreading ramstage-y += model_f2x_init.c diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 1f2b564..c855996 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,5 +1,8 @@ ramstage-y += model_f3x_init.c + +subdirs-y += ../hyperthreading subdirs-y += ../smm/gen1 + ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index 46312ce..9268def 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/p4-netburst/cache_as_ram.S diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 2af44bd..2c18f66 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/core2/cache_as_ram.S diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index fd2c9d8..7904e17 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/bootblock.c diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 8cc9a94..9b571f5 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/p4-netburst/cache_as_ram.S diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 84fc7a2..4fd01ac 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/core2/cache_as_ram.S diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 9fc9d15..32bb474 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 8e3cb2c..4156052 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../microcode -subdirs-y += ../hyperthreading subdirs-y += ../speedstep bootblock-y += ../car/core2/cache_as_ram.S -- To view, visit https://review.coreboot.org/c/coreboot/+/55201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4956493d8c0c6b922343e060d2d2bd0ec20f5bb6 Gerrit-Change-Number: 55201 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Avoid aliasing MMIO writes
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55200 ) Change subject: cpu/x86/lapic: Avoid aliasing MMIO writes ...................................................................... cpu/x86/lapic: Avoid aliasing MMIO writes Change-Id: I75440cb0742eeaa140f49e7e4a4c51a96465441b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/55200/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index dc61ea7..645bfdc 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -6,6 +6,7 @@ #include <stdint.h> int x2apic_mode_enabled; +uintptr_t lapic_default_base = LAPIC_DEFAULT_BASE; uintptr_t cpu_get_lapic_addr(void) { diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 30c12e8..4c3fe6b 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -10,15 +10,22 @@ #include <smp/node.h> extern int x2apic_mode_enabled; +extern uintptr_t lapic_default_base; + +union lapic_registers { + uint32_t reg32[0x400 / sizeof(uint32_t)]; +}; static __always_inline uint32_t xapic_read(unsigned int reg) { - return read32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg)); + volatile union lapic_registers *xapic_mmio = (void *)lapic_default_base; + return xapic_mmio->reg32[reg / sizeof(uint32_t)]; } static __always_inline void xapic_write(unsigned int reg, uint32_t v) { - write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); + volatile union lapic_registers *xapic_mmio = (void *)lapic_default_base; + xapic_mmio->reg32[reg / sizeof(uint32_t)] = v; } static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) -- To view, visit https://review.coreboot.org/c/coreboot/+/55200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75440cb0742eeaa140f49e7e4a4c51a96465441b Gerrit-Change-Number: 55200 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic()
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55199 ) Change subject: [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic() ...................................................................... [RFC,WIP] cpu/x86/lapic: Drop xapic_write_atomic() The memory clobber impacts code generator. In linux kernel, the errata or quick X86_BUG_11AP is documented to be specific quirk for Intel model 0x520. Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 2 files changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/55199/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 22647bc..fe1c824 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -128,7 +128,7 @@ printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk(BIOS_ERR, "Try to reset ESR\n"); - xapic_write_atomic(LAPIC_ESR, 0); + lapic_write(LAPIC_ESR, 0); printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); } diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 3c860ab..30c12e8 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -21,21 +21,10 @@ write32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg), v); } -static inline void xapic_write_atomic(unsigned long reg, uint32_t v) -{ - volatile uint32_t *ptr; - - ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE + reg); - - asm volatile ("xchgl %0, %1\n" - : "+r" (v), "+m" (*(ptr)) - : : "memory", "cc"); -} - static __always_inline void xapic_send_ipi(uint32_t icrlow, uint32_t apicid) { - xapic_write_atomic(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - xapic_write_atomic(LAPIC_ICR, icrlow); + xapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + xapic_write(LAPIC_ICR, icrlow); } static __always_inline int xapic_busy(void) @@ -115,7 +104,7 @@ value = xapic_read(reg); value &= mask; value |= or; - xapic_write_atomic(reg, value); + xapic_write(reg, value); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/55199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec10335f603674bcef2e7494831cf11200795d38 Gerrit-Change-Number: 55199 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [RFC,WIP] cpu/x86/lapic: Evaluate x2apic_mode just once
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55198 ) Change subject: [RFC,WIP] cpu/x86/lapic: Evaluate x2apic_mode just once ...................................................................... [RFC,WIP] cpu/x86/lapic: Evaluate x2apic_mode just once TBD: Actually set and test. Change-Id: Iff4f5dc50999f977eaf9b32e7caebf098a3600fe Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 3 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/55198/1 diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 5ec234b..7d2f952 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-y += lapic.c +all-y += lapic.c ramstage-$(CONFIG_AP_IN_SIPI_WAIT) += lapic_cpu_stop.c ramstage-$(CONFIG_LEGACY_CPU_INIT) += lapic_cpu_init.c ramstage-$(CONFIG_LEGACY_CPU_INIT) += secondary.S diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 3c0273e..dc61ea7 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -5,6 +5,8 @@ #include <console/console.h> #include <stdint.h> +int x2apic_mode_enabled; + uintptr_t cpu_get_lapic_addr(void) { return LAPIC_DEFAULT_BASE; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 583d72a..3c860ab 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -7,6 +7,9 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <stdint.h> +#include <smp/node.h> + +extern int x2apic_mode_enabled; static __always_inline uint32_t xapic_read(unsigned int reg) { @@ -78,9 +81,7 @@ if (CONFIG(X2APIC_ONLY)) return true; - msr_t msr; - msr = rdmsr(LAPIC_BASE_MSR); - return ((msr.lo & LAPIC_BASE_X2APIC_ENABLED) == LAPIC_BASE_X2APIC_ENABLED); + return x2apic_mode_enabled; } static __always_inline uint32_t lapic_read(unsigned int reg) @@ -147,6 +148,8 @@ msr.lo &= ~LAPIC_BASE_MSR_X2APIC_MODE; if (CONFIG(X2APIC_ONLY)) msr.lo |= LAPIC_BASE_MSR_X2APIC_MODE; + if (CONFIG(X2APIC_RUNTIME) && boot_cpu()) + x2apic_mode_enabled = !!(msr.lo & LAPIC_BASE_MSR_X2APIC_MODE); wrmsr(LAPIC_BASE_MSR, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff4f5dc50999f977eaf9b32e7caebf098a3600fe Gerrit-Change-Number: 55198 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mp_init: Support both xapic and x2apic with common code
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55197 to review the following change. Change subject: cpu/x86/mp_init: Support both xapic and x2apic with common code ...................................................................... cpu/x86/mp_init: Support both xapic and x2apic with common code Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/mp_init.c 1 file changed, 14 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/55197/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index ad45ee9..d7c2f7f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -435,27 +435,8 @@ printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count); - if (is_x2apic_mode()) { - x2apic_send_ipi(LAPIC_DM_INIT | LAPIC_INT_LEVELTRIG | - LAPIC_INT_ASSERT | LAPIC_DEST_ALLBUT, 0); - mdelay(10); - x2apic_send_ipi(LAPIC_DM_STARTUP | LAPIC_INT_LEVELTRIG | - LAPIC_DEST_ALLBUT | sipi_vector, 0); - - /* Wait for CPUs to check in up to 200 us. */ - wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */); - - x2apic_send_ipi(LAPIC_DM_STARTUP | LAPIC_INT_LEVELTRIG | - LAPIC_DEST_ALLBUT | sipi_vector, 0); - - /* Wait for CPUs to check in. */ - if (wait_for_aps(num_aps, ap_count, 100000 /* 100 ms */, 50 /* us */)) { - printk(BIOS_ERR, "Not all APs checked in: %d/%d.\n", - atomic_read(num_aps), ap_count); - return -1; - } - return 0; - } + int x2apic_mode = is_x2apic_mode(); + printk(BIOS_DEBUG, "Starting CPUs in %s mode\n", x2apic_mode ? "x2apic" : "xapic"); if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); @@ -671,11 +652,6 @@ void smm_initiate_relocation_parallel(void) { - if (is_x2apic_mode()) { - x2apic_send_ipi(LAPIC_DM_SMI | LAPIC_INT_LEVELTRIG, lapicid()); - return; - } - if (lapic_busy()) { printk(BIOS_DEBUG, "Waiting for ICR not to be busy..."); if (apic_wait_timeout(1000 /* 1 ms */, 50)) { @@ -685,11 +661,19 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); - if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) - printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); + /* FIXME: Why the difference? */ + if (is_x2apic_mode()) + lapic_send_ipi(LAPIC_DM_SMI | LAPIC_INT_LEVELTRIG, lapicid()); else - printk(BIOS_DEBUG, "Relocation complete.\n"); + lapic_send_ipi(LAPIC_INT_ASSERT | LAPIC_DM_SMI, lapicid()); + + if (lapic_busy()) { + if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) { + printk(BIOS_DEBUG, "SMI Relocation timed out.\n"); + return; + } + } + printk(BIOS_DEBUG, "Relocation complete.\n"); } DECLARE_SPIN_LOCK(smm_relocation_lock); -- To view, visit https://review.coreboot.org/c/coreboot/+/55197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265 Gerrit-Change-Number: 55197 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86: Default to PARALLEL_MP selected
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Damien Zammit, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55196 ) Change subject: cpu/x86: Default to PARALLEL_MP selected ...................................................................... cpu/x86: Default to PARALLEL_MP selected Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 31 files changed, 17 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55196/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 0d3d132..8d08bd9 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -16,7 +16,6 @@ #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select HAVE_ASAN_IN_ROMSTAGE diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 04b9e67..31105ec 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -16,7 +16,6 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select PARALLEL_MP config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 5098ac7..cf6a907 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -16,7 +16,6 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE - select PARALLEL_MP config SMM_TSEG_SIZE hex diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 85f99e9..36700e7 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -15,10 +15,10 @@ config CPU_QEMU_X86_LAPIC_INIT bool "Legacy serial LAPIC init" + select LEGACY_CPU_INIT config CPU_QEMU_X86_PARALLEL_MP bool "Parallel MP init" - select PARALLEL_MP endchoice diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index e535eeb..c769865 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -4,7 +4,8 @@ default n config PARALLEL_MP - def_bool n + def_bool y + depends on !LEGACY_CPU_INIT help This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism @@ -17,6 +18,9 @@ Allow APs to do other work after initialization instead of going to sleep. +config LEGACY_CPU_INIT + bool + choice LAPIC_ACCESS_MODE prompt "APIC operation mode" default XAPIC_ONLY @@ -28,12 +32,12 @@ config X2APIC_ONLY prompt "Set X2APIC mode" bool - depends on PARALLEL_MP + depends on !LEGACY_CPU_INIT config X2APIC_RUNTIME prompt "Support both XAPIC and X2APIC" bool - depends on PARALLEL_MP + depends on !LEGACY_CPU_INIT endchoice diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index c0adcfc..5ec234b 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,7 +1,8 @@ ramstage-y += lapic.c -ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_AP_IN_SIPI_WAIT) += lapic_cpu_stop.c -ramstage-$(CONFIG_SMP) += secondary.S +ramstage-$(CONFIG_LEGACY_CPU_INIT) += lapic_cpu_init.c +ramstage-$(CONFIG_LEGACY_CPU_INIT) += secondary.S + bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 9c7eb92..c01756a 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool + select LEGACY_CPU_INIT select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 60007a3..b4a4399 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool + select LEGACY_CPU_INIT select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index d1ccbb5..8096305 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool + select LEGACY_CPU_INIT select RESOURCE_ALLOCATOR_V3 if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 6d321e9..c30b464 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -2,6 +2,7 @@ config NORTHBRIDGE_AMD_PI_00730F01 bool + select LEGACY_CPU_INIT if NORTHBRIDGE_AMD_PI_00730F01 diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index d222e2e..36bceb3 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -10,5 +10,6 @@ select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE + select LEGACY_CPU_INIT endif diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index cd3e27c..daf96aa 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -12,7 +12,6 @@ select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF - select PARALLEL_MP config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index ff8e2ae..e8d16a1 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -5,6 +5,7 @@ select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select NO_CBFS_MCACHE + select LEGACY_CPU_INIT config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 2af4424..51ee320 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -13,7 +13,6 @@ select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT - select PARALLEL_MP config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 0ff437a..f85cd2e 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -13,7 +13,6 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI - select PARALLEL_MP select NO_CBFS_MCACHE config VGA_BIOS_ID diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 99f6d79..3ebb4fa 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -11,7 +11,6 @@ select VGA select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS - select PARALLEL_MP select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config CBFS_SIZE diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 075404b66..568d8ba 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -28,7 +28,6 @@ select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select IOAPIC - select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e9ed845..594ed75 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -57,7 +57,6 @@ select SOC_AMD_COMMON_BLOCK_UCODE select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER select SSE2 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index ccffe76..7594bd8 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -20,7 +20,6 @@ select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS select IOAPIC - select PARALLEL_MP select PARALLEL_MP_AP_WORK select RTC select SOC_AMD_PI diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 79e775d..a146a77 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -36,7 +36,6 @@ select INTEL_TME select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 9fe2c29..45414a4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -46,7 +46,6 @@ select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_XIP_EARLY_STAGES - select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 8811b38..a9ba092 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -19,7 +19,6 @@ select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT - select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 0e1b6db..f91e7de 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -16,7 +16,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER - select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 8c6cd53..aa5e5e9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -68,7 +68,6 @@ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PM_ACPI_TIMER_OPTIONAL diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index aa5c345..f6bafae 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -23,7 +23,6 @@ select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS - select PARALLEL_MP select PCR_COMMON_IOSF_1_0 select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index a522db5..bb1766a 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -28,7 +28,6 @@ select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index cb4ef49..71e2bee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -28,7 +28,6 @@ select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 80fc164..f019026 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -29,7 +29,6 @@ select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3f02974..0117b0b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -43,7 +43,6 @@ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PM_ACPI_TIMER_OPTIONAL diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 0c472d9..eb0fea9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -32,7 +32,6 @@ select IOAPIC select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT - select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_2 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 09f72a3..6d3917f 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -35,7 +35,6 @@ select FSP_M_XIP select POSTCAR_STAGE select IOAPIC - select PARALLEL_MP select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/55196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Gerrit-Change-Number: 55196 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Drop read/write_around aliases
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55195 ) Change subject: cpu/x86/lapic: Drop read/write_around aliases ...................................................................... cpu/x86/lapic: Drop read/write_around aliases Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/55195/1 diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 3a164a6..22647bc 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -128,7 +128,7 @@ printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk(BIOS_ERR, "Try to reset ESR\n"); - lapic_write_around(LAPIC_ESR, 0); + xapic_write_atomic(LAPIC_ESR, 0); printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); } @@ -157,7 +157,7 @@ for (j = 1; j <= CONFIG_NUM_IPI_STARTS; j++) { printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid); - lapic_read_around(LAPIC_SPIV); + lapic_read(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); lapic_read(LAPIC_ESR); printk(BIOS_SPEW, "After apic_write.\n"); @@ -185,7 +185,7 @@ * Due to the Pentium erratum 3AP. */ if (maxlvt > 3) { - lapic_read_around(LAPIC_SPIV); + lapic_read(LAPIC_SPIV); lapic_write(LAPIC_ESR, 0); } accept_status = (lapic_read(LAPIC_ESR) & 0xEF); diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index b6d4330..583d72a 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -40,9 +40,6 @@ return xapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } -#define lapic_read_around(x) lapic_read(x) -#define lapic_write_around(x, y) xapic_write_atomic((x), (y)) - static __always_inline uint32_t x2apic_read(unsigned int reg) { uint32_t value, index; -- To view, visit https://review.coreboot.org/c/coreboot/+/55195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab Gerrit-Change-Number: 55195 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Replace LOCAL_APIC_ADDR references
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55194 ) Change subject: cpu/x86/lapic: Replace LOCAL_APIC_ADDR references ...................................................................... cpu/x86/lapic: Replace LOCAL_APIC_ADDR references Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/smp/mpspec.h M src/arch/x86/mpspec.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/smm/smmhandler.S M src/include/cpu/x86/lapic_def.h M src/mainboard/apple/macbook21/mptable.c M src/mainboard/asus/a88xm-e/mptable.c M src/mainboard/asus/p2b/variants/p2b-d/mptable.c M src/mainboard/asus/p2b/variants/p2b-ds/mptable.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/getac/p470/mptable.c M src/mainboard/ibase/mb899/mptable.c M src/mainboard/intel/d945gclf/mptable.c M src/mainboard/kontron/986lcd-m/mptable.c M src/mainboard/lenovo/t60/mptable.c M src/mainboard/lenovo/x60/mptable.c M src/mainboard/roda/rk886ex/mptable.c M src/soc/amd/cezanne/data_fabric.c M src/soc/amd/picasso/data_fabric.c M src/soc/amd/stoneyridge/northbridge.c 21 files changed, 29 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/55194/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 07bd7b5..c929e5e 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -340,8 +340,3 @@ } return -1; } - -uintptr_t cpu_get_lapic_addr(void) -{ - return LOCAL_APIC_ADDR; -} diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index 25c23e6..198d7df 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -224,7 +224,7 @@ */ } __packed; -void mptable_init(struct mp_config_table *mc, u32 lapic_addr); +void mptable_init(struct mp_config_table *mc); void *smp_next_mpc_entry(struct mp_config_table *mc); void *smp_next_mpe_entry(struct mp_config_table *mc); diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 15c3c0e..fa29e80 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -6,13 +6,15 @@ #include <arch/smp/mpspec.h> #include <string.h> #include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/x86/lapic.h> #include <drivers/generic/ioapic/chip.h> /* Initialize the specified "mc" struct with initial values. */ -void mptable_init(struct mp_config_table *mc, u32 lapic_addr) +void mptable_init(struct mp_config_table *mc) { int i; + u32 lapic_addr = cpu_get_lapic_addr(); memset(mc, 0, sizeof(*mc)); @@ -533,7 +535,7 @@ v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 468a5dc..3c0273e 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -1,9 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <stdint.h> +uintptr_t cpu_get_lapic_addr(void) +{ + return LAPIC_DEFAULT_BASE; +} + void lapic_virtual_wire_mode_init(void) { /* this is so interrupts work. This is very limited scope -- diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 4cbfbfd..3750e52 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -126,8 +126,9 @@ movw %ax, %fs movw %ax, %gs + /* FIXME: Incompatible with X2APIC_SUPPORT. */ /* Get this CPU's LAPIC ID */ - movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi + movl $(LAPIC_DEFAULT_BASE | LAPIC_ID), %esi movl (%esi), %ecx shr $24, %ecx diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index d5e863a..84a3413 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -9,12 +9,7 @@ (LAPIC_BASE_MSR_X2APIC_MODE | LAPIC_BASE_MSR_ENABLE) #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 -#ifndef LOCAL_APIC_ADDR -#define LOCAL_APIC_ADDR 0xfee00000 -#endif -#ifndef LAPIC_DEFAULT_BASE -#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR -#endif +#define LAPIC_DEFAULT_BASE 0xfee00000 #define LAPIC_ID 0x020 #define LAPIC_LVR 0x030 diff --git a/src/mainboard/apple/macbook21/mptable.c b/src/mainboard/apple/macbook21/mptable.c index 67827e2..22c58af 100644 --- a/src/mainboard/apple/macbook21/mptable.c +++ b/src/mainboard/apple/macbook21/mptable.c @@ -11,7 +11,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c index b9e743c..1027391 100644 --- a/src/mainboard/asus/a88xm-e/mptable.c +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -39,7 +39,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c index 590c889..98525bb 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-d/mptable.c @@ -10,7 +10,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c index b8787c8..f2d3a85 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b/variants/p2b-ds/mptable.c @@ -10,7 +10,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index fcff7bc..8579b8f 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -155,7 +155,7 @@ /* Reserve space for the LAPIC. There's one in every processor, but * the space only needs to be reserved once, so we do it here. */ res = new_resource(dev, 3); - res->base = LOCAL_APIC_ADDR; + res->base = cpu_get_lapic_addr(); res->size = 0x10000UL; res->limit = 0xffffffffUL; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 603f1ba..1d259fa 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -11,7 +11,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 7c632f5..bfd29ae 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -14,7 +14,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index 1b6a1b1..30b41dc 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -11,7 +11,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 0c4ec67..54faae5 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -13,7 +13,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 2dc3a1a..fbc239f 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -11,7 +11,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 9e2cff1..9efb240 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -11,7 +11,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index 0ec750c..125a050 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -11,7 +11,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LOCAL_APIC_ADDR); + mptable_init(mc); smp_write_processors(mc); diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c index d603c8a..1a0f9cb 100644 --- a/src/soc/amd/cezanne/data_fabric.c +++ b/src/soc/amd/cezanne/data_fabric.c @@ -37,7 +37,7 @@ int reg; uint32_t base, limit, ctrl; const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; data_fabric_print_mmio_conf(); diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index 700cb84..b5949f0 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -37,7 +37,7 @@ int reg; uint32_t base, limit, ctrl; const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LOCAL_APIC_ADDR - 1) >> D18F0_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; data_fabric_print_mmio_conf(); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index eb59cdc..0df9d97 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -362,7 +362,7 @@ /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; - limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; + limit = (ALIGN_DOWN(LAPIC_DEFAULT_BASE - 1, 64 * KiB) >> 8) | MMIO_NP; pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); -- To view, visit https://review.coreboot.org/c/coreboot/+/55194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Gerrit-Change-Number: 55194 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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