coreboot-gerrit June 2021

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Change in coreboot[master]: arch/x86/ioapic: Split some ioapic utility functions
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55183 ) Change subject: arch/x86/ioapic: Split some ioapic utility functions ...................................................................... arch/x86/ioapic: Split some ioapic utility functions Change-Id: I70dfec900e8ce6630e61bc3fcbcfd88c097a5600 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/ioapic.c 1 file changed, 40 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/55183/1 diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 5e3e2af..1a8b489 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <device/mmio.h> #include <arch/ioapic.h> #include <console/console.h> @@ -21,7 +22,7 @@ { /* Read the available number of interrupts. */ int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; - if (ioapic_interrupts == 0xff) + if (!ioapic_interrupts || ioapic_interrupts == 0xff) ioapic_interrupts = 23; ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection entry, which is the number of interrupts @@ -31,23 +32,21 @@ return ioapic_interrupts; } -void clear_ioapic(void *ioapic_base) +static void clear_vectors(void *ioapic_base, u8 first, u8 last) { u32 low, high; - u32 i, ioapic_interrupts; + u8 i; printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base); - ioapic_interrupts = ioapic_interrupt_count(ioapic_base); - low = INT_DISABLED; high = NONE; - for (i = 0; i < ioapic_interrupts; i++) { + for (i = first; i <= last; i++) { io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", + printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n", i, high, low); } @@ -57,15 +56,42 @@ } } -void set_ioapic_id(void *ioapic_base, u8 ioapic_id) +void clear_ioapic(void *ioapic_base) +{ + clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1); +} + +static void route_i8259_irq0(void *ioapic_base) { u32 bsp_lapicid = lapicid(); + u32 low, high; + + ASSERT(bsp_lapicid < 255); + + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", + bsp_lapicid); + + /* Enable Virtual Wire Mode. Should this be LOGICAL_DEST instead? */ + low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + high = bsp_lapicid << (56 - 32); + + io_apic_write(ioapic_base, 0x10, low); + io_apic_write(ioapic_base, 0x11, high); + + if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { + printk(BIOS_WARNING, "IOAPIC not responding.\n"); + return; + } + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); +} + +void set_ioapic_id(void *ioapic_base, u8 ioapic_id) +{ int i; printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", ioapic_base); - printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); if (ioapic_id) { printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); @@ -84,11 +110,7 @@ static void load_vectors(void *ioapic_base) { - u32 bsp_lapicid = lapicid(); - u32 low, high; - u32 i, ioapic_interrupts; - - ioapic_interrupts = ioapic_interrupt_count(ioapic_base); + int first = 1, last; if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) { /* @@ -104,29 +126,10 @@ io_apic_write(ioapic_base, 0x03, 0); } - /* Enable Virtual Wire Mode. */ - low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; - high = bsp_lapicid << (56 - 32); + route_i8259_irq0(ioapic_base); - io_apic_write(ioapic_base, 0x10, low); - io_apic_write(ioapic_base, 0x11, high); - - if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { - printk(BIOS_WARNING, "IOAPIC not responding.\n"); - return; - } - - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - 0, high, low); - low = INT_DISABLED; - high = NONE; - for (i = 1; i < ioapic_interrupts; i++) { - io_apic_write(ioapic_base, i * 2 + 0x10, low); - io_apic_write(ioapic_base, i * 2 + 0x11, high); - - printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); - } + last = ioapic_interrupt_count(ioapic_base) - 1; + clear_vectors(ioapic_base, first, last); } void setup_ioapic(void *ioapic_base, u8 ioapic_id) -- To view, visit https://review.coreboot.org/c/coreboot/+/55183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70dfec900e8ce6630e61bc3fcbcfd88c097a5600 Gerrit-Change-Number: 55183 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Fix X2APIC NMI entry in ACPI MADT
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55182 ) Change subject: soc/intel/common: Fix X2APIC NMI entry in ACPI MADT ...................................................................... soc/intel/common: Fix X2APIC NMI entry in ACPI MADT Change-Id: I9c0537a3efba942329f80d7cfdbd910b8958516f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55182/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index d7a0e8e..ea2a778 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -83,7 +83,7 @@ if (is_x2apic_mode()) current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, - 0xff, 0xd, 1); + 0xffffffff, 0xd, 1); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/55182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c0537a3efba942329f80d7cfdbd910b8958516f Gerrit-Change-Number: 55182 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55073 to look at the new patch set (#2). Change subject: cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE ...................................................................... cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODE Allows compile-time optimisation on platforms that do not wish to enable runtime checking of X2APIC. Legacy lapic_cpu_init() is incompatible so there is dependency on PARALLEL_MP. Also stop_this_cpu() is incompatible, so there is dependency on !AP_IN_SIPI_WAIT. Since the code actually lacks enablement of X2APIC (apparently assuming the blob has done it) and the other small flaws pointed out in earlier reviews, X2APIC_RUNTIME is not selected per default on any platform yet. Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/55073/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f Gerrit-Change-Number: 55073 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Apply more uses for Kconfig TPM
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55016 ) Change subject: Apply more uses for Kconfig TPM ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Gerrit-Change-Number: 55016 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 08:13:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add LTE modem support for drawper
by Tony Huang (Code Review) 04 Jun '21

04 Jun '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55181 to look at the new patch set (#3). Change subject: mb/google/dedede/var/drawcia: Add LTE modem support for drawper ...................................................................... mb/google/dedede/var/drawcia: Add LTE modem support for drawper Add LTE modem to devicetree Configure GPIO control for LTE modem BUG=b:186393848 TEST=Built image and verified with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/Makefile.inc M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/variant.c 4 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/55181/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Gerrit-Change-Number: 55181 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add LTE modem support for drawper
by Tony Huang (Code Review) 04 Jun '21

04 Jun '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55181 to look at the new patch set (#2). Change subject: mb/google/dedede/var/drawcia: Add LTE modem support for drawper ...................................................................... mb/google/dedede/var/drawcia: Add LTE modem support for drawper Add LTE modem to devicetree Configure GPIO control for LTE modem BUG=b:186393848 TEST=Built image and verified with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/variant.c 3 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/55181/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Gerrit-Change-Number: 55181 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add LTE modem support for drawper
by Tony Huang (Code Review) 04 Jun '21

04 Jun '21

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55181 ) Change subject: mb/google/dedede/var/drawcia: Add LTE modem support for drawper ...................................................................... mb/google/dedede/var/drawcia: Add LTE modem support for drawper Add LTE modem to devicetree Configure GPIO control for LTE modem BUG=b:186393848 TEST=Built image and verified with command modem status Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/drawcia/gpio.c M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/55181/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/gpio.c b/src/mainboard/google/dedede/variants/drawcia/gpio.c index 96b64cc..279c891 100644 --- a/src/mainboard/google/dedede/variants/drawcia/gpio.c +++ b/src/mainboard/google/dedede/variants/drawcia/gpio.c @@ -16,8 +16,20 @@ /* bid6: Pad configuration for board version 6 or 8 in ramstage*/ static const struct pad_config board6or8_gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ + PAD_CFG_GPO(GPP_B7, 1, DEEP), + /* C12 : AP_PEN_DET_ODL has an external pull-up and hence no pad termination.*/ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* H0 : WWAN_PERST */ + PAD_CFG_GPO(GPP_H0, 0, PLTRST), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index e157894..e3900c6 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -144,10 +144,25 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 2.3 on end + end + chip drivers/usb/acpi register "desc" = ""Camera"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.5 on end end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end end end end # USB xHCI -- To view, visit https://review.coreboot.org/c/coreboot/+/55181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20450ae37e5047dba67211316515994bd2a09600 Gerrit-Change-Number: 55181 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios
by Vinay Kumar (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: V Sowmya. Vinay Kumar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54055 ) Change subject: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios ...................................................................... Patch Set 6: (1 comment) This change is ready for review. File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54055/comment/e0e815fa_1744673e PS6, Line 315: params->IccMax[1] = 40; These IccMax values are in 1/4 units and 282 SKU requires 80A and 40A. So these need to be changed to 320A and 160A respectively for Core and GT Iccmax. Please check and fix this. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/54055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d485872c8bae32f83ebf94bdaa4c6a793976ce7 Gerrit-Change-Number: 54055 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 07:40:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offsets
by Yu-Ping Wu (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 ) Change subject: soc/mediatek/mt8195: fix GPIO register offsets ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55163/comment/be867da9_b6c378b1 PS4, Line 10: > I add document info in commit message. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91 Gerrit-Change-Number: 55163 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 07:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Support Realtek audio codec ALC5682I and speaker L/R
by Kirk Wang (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Wayne3 Wang, Henry Sun, Ariel Chang, Paul Menzel, Paul2 Huang, Alex1 Kao, Karthik Ramasubramanian. Kirk Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54529 ) Change subject: mb/google/dedede: Support Realtek audio codec ALC5682I and speaker L/R ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8173ffbfb1a8f18978a5e35c69972d4a6d8cb04a Gerrit-Change-Number: 54529 Gerrit-PatchSet: 11 Gerrit-Owner: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 07:37:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2021