build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55189 )
Change subject: cpu/x86/lapic: Redo DEBUG_HALT_SELF
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/lapic/lapic_cpu_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120695):
https://review.coreboot.org/c/coreboot/+/55189/comment/9870e793_1f7ae471
PS1, Line 321: #define dprintk(LEVEL, args...) do { printk(LEVEL, ##args); } while (0)
Single statement macros should not use a do {} while (0) loop
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7e42519d5bcee95970d366fd64923de874098172
Gerrit-Change-Number: 55189
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Fri, 04 Jun 2021 08:42:23 +0000
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Attention is currently required from: V Sowmya, Furquan Shaikh, Tim Wawrzynczak, Angel Pons.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55207 )
Change subject: mb/intel/sm: Skip FSP to program UART0
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
@Sowmya, can you please try this one in SM if you have handy, this is right configuration for UART0
--
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Gerrit-Change-Number: 55207
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
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Gerrit-Comment-Date: Fri, 04 Jun 2021 08:42:20 +0000
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55206 )
Change subject: mb/intel/sm: Use device aliases
......................................................................
mb/intel/sm: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
1 file changed, 40 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/55206/1
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 43a23a1..4dd0ca5 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -174,21 +174,17 @@
}"
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Graphics
- device pci 04.0 on end # DPTF
- device pci 05.0 on end # IPU
- device pci 06.0 off end # PEG60
- device pci 07.0 on end # TBT_PCIe0
- device pci 07.1 on end # TBT_PCIe1
- device pci 07.2 on end # TBT_PCIe2
- device pci 07.3 on end # TBT_PCIe3
- device pci 08.0 off end # GNA
- device pci 09.0 off end # NPK
- device pci 0a.0 off end # Crash-log SRAM
- device pci 0d.0 on end # USB xHCI
- device pci 0d.1 off end # USB xDCI (OTG)
- device pci 0d.2 on
+ device ref igpu on end
+ device ref dtt on end
+ device ref ipu on end
+ device ref ipu on end
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp1 on end
+ device ref tbt_pcie_rp2 on end
+ device ref tbt_pcie_rp3 on end
+ device ref crashlog off end
+ device ref tcss_xhci on end
+ device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp" = "{
[0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H19),},
@@ -196,24 +192,8 @@
device generic 0 on end
end
end
- device pci 0d.3 on end # TBT DMA1
- device pci 0e.0 off end # VMD
- device pci 10.0 off end
- device pci 10.1 off end
- device pci 10.6 off end # THC0
- device pci 10.7 off end # THC1
- device pci 11.0 off end
- device pci 11.1 off end
- device pci 11.2 off end
- device pci 11.3 off end
- device pci 11.4 off end
- device pci 11.5 off end
- device pci 12.0 off end # SensorHUB
- device pci 12.5 off end
- device pci 12.6 off end # GSPI2
- device pci 13.0 off end # GSPI3
- device pci 13.1 off end
- device pci 14.0 on
+ device ref tcss_dma1 on end
+ device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
@@ -227,18 +207,16 @@
end
end
end
- end # USB3.1 xHCI
- device pci 14.1 off end # USB3.1 xDCI
- device pci 14.2 off end # Shared RAM
- device pci 14.3 on
+ end
+ device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
- end # CNVi: WiFi
- device pci 15.0 on end # I2C0
- device pci 15.1 on end # I2C1
- device pci 15.2 on
+ end
+ device ref i2c0 on end
+ device ref i2c1 on end
+ device ref i2c2 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
@@ -267,17 +245,11 @@
register "name" = ""MAXL""
device i2c 32 on end
end
- end # I2C2
- device pci 15.3 on end # I2C3
- device pci 16.0 on end # HECI1
- device pci 16.1 off end # HECI2
- device pci 16.2 off end # CSME
- device pci 16.3 off end # CSME
- device pci 16.4 off end # HECI3
- device pci 16.5 off end # HECI4
- device pci 17.0 on end # SATA
- device pci 19.0 off end # I2C4
- device pci 19.1 on
+ end
+ device ref i2c3 on end
+ device ref heci1 on end
+ device ref sata on end
+ device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
@@ -286,46 +258,34 @@
register "probed" = "1"
device i2c 15 on end
end
- end # I2C5
- device pci 19.2 off end # UART2
- device pci 1c.0 off end # RP1
- device pci 1c.1 off end # RP2
- device pci 1c.2 off end # RP3
- device pci 1c.3 off end # RP4
- device pci 1c.4 on end # RP5
- device pci 1c.5 off end # RP6
- device pci 1c.6 off end # RP7
- device pci 1c.7 on
+ end
+ device ref pcie_rp5 on end
+ device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
register "srcclk_pin" = "3"
device generic 0 on end
end
- end # RP8
- device pci 1d.0 on end # RP9
- device pci 1d.1 off end # RP10
- device pci 1d.2 off end # RP11
- device pci 1d.3 off end # RP12
- device pci 1e.0 on end # UART0
- device pci 1e.1 off end # UART1
- device pci 1e.2 on
+ end
+ device ref pcie_rp9 on end
+ device ref uart0 on end
+ device ref gspi0 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C3_IRQ)"
device spi 0 on end
end
- end # GSPI0
- device pci 1e.3 off end # GSPI1
- device pci 1f.0 on
+ end
+ device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
- end # eSPI
- device pci 1f.1 on end # P2SB
- device pci 1f.2 hidden
+ end
+ device ref p2sb on end
+ device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
chip drivers/intel/pmc_mux
@@ -346,10 +306,9 @@
end
end
end
- end # PMC
- device pci 1f.3 on end # Intel Audio SNDW
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # SPI
- device pci 1f.6 off end # GbE
+ end
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Gerrit-Change-Number: 55206
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange
Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/55205 )
Change subject: mb/intel/adlrvp: Use device aliases
......................................................................
mb/intel/adlrvp: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
4 files changed, 88 insertions(+), 167 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/55205/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Gerrit-Change-Number: 55205
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newpatchset
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55205 )
Change subject: mb/intel/adlrvp: Use device aliases
......................................................................
mb/intel/adlrvp: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
4 files changed, 88 insertions(+), 167 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/55205/1
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 23913cc..cd6c265 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -204,10 +204,9 @@
}"
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 on end # PEG10
- device pci 02.0 on end # Graphics
- device pci 04.0 on
+ device ref pcie5 on end
+ device ref igpu on end
+ device ref dtt on
chip drivers/intel/dptf
## sensor information
@@ -301,38 +300,19 @@
device generic 0 on end
end
- end # DPTF
- device pci 05.0 on end # IPU
- device pci 06.0 on end # PEG60
- device pci 06.2 on end # PEG62
- device pci 07.0 on end # TBT_PCIe0
- device pci 07.1 on end # TBT_PCIe1
- device pci 07.2 on end # TBT_PCIe2
- device pci 07.3 on end # TBT_PCIe3
- device pci 08.0 off end # GNA
- device pci 09.0 off end # NPK
- device pci 0a.0 off end # Crash-log SRAM
- device pci 0d.0 on end # USB xHCI
- device pci 0d.1 on end # USB xDCI (OTG)
- device pci 0d.2 on end # TBT DMA0
- device pci 0d.3 on end # TBT DMA1
- device pci 0e.0 off end # VMD
- device pci 10.0 off end
- device pci 10.1 off end
- device pci 10.6 off end # THC0
- device pci 10.7 off end # THC1
- device pci 11.0 off end
- device pci 11.1 off end
- device pci 11.2 off end
- device pci 11.3 off end
- device pci 11.4 off end
- device pci 11.5 off end
- device pci 12.0 off end # SensorHUB
- device pci 12.5 off end
- device pci 12.6 off end # GSPI2
- device pci 13.0 off end # GSPI3
- device pci 13.1 off end
- device pci 14.0 on
+ end
+ device ref ipu on end
+ device ref pcie4_0 on end
+ device ref pcie4_1 on end
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp1 on end
+ device ref tbt_pcie_rp2 on end
+ device ref tbt_pcie_rp3 on end
+ device ref tcss_xhci on end
+ device ref tcss_xdci on end
+ device ref tcss_dma0 on end
+ device ref tcss_dma1 on end
+ device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
@@ -344,49 +324,34 @@
end
end
end
- end # USB3.1 xHCI
- device pci 14.1 off end # USB3.1 xDCI
- device pci 14.2 off end # Shared RAM
- device pci 14.3 on
+ end
+ device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
- end # CNVi: WiFi
- device pci 15.0 on end # I2C0
- device pci 15.1 on end # I2C1
- device pci 15.2 on end # I2C2
- device pci 15.3 on end # I2C3
- device pci 16.0 on end # HECI1
- device pci 16.1 off end # HECI2
- device pci 16.2 off end # CSME
- device pci 16.3 off end # CSME
- device pci 16.4 off end # HECI3
- device pci 16.5 off end # HECI4
- device pci 17.0 on end # SATA
- device pci 19.0 off end # I2C4
- device pci 19.1 on end # I2C5
- device pci 19.2 off end # UART2
- device pci 1c.0 on end # RP1
- device pci 1c.1 off end # RP2
- device pci 1c.2 on end # RP3 # W/A to FSP issue
- device pci 1c.3 on end # RP4 # W/A to FSP issue
- device pci 1c.4 on end # RP5
- device pci 1c.5 on end # RP6
- device pci 1c.6 off end # RP7
- device pci 1c.7 on end # RP8
- device pci 1d.0 on end # RP9
- device pci 1d.1 off end # RP10
- device pci 1d.2 on end # RP11
- device pci 1d.3 off end # RP12
- device pci 1e.0 on end # UART0
- device pci 1e.1 off end # UART1
- device pci 1e.2 on end # GSPI0
- device pci 1e.3 off end # GSPI1
- device pci 1f.0 on end # eSPI
- device pci 1f.1 on end # P2SB
- device pci 1f.2 hidden end # PMC
- device pci 1f.3 on
+ end
+ device ref i2c0 on end
+ device ref i2c1 on end
+ device ref i2c2 on end
+ device ref i2c3 on end
+ device ref heci1 on end
+ device ref sata on end
+ device ref i2c5 on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp8 on end
+ device ref pcie_rp9 on end
+ device ref pcie_rp11 on end
+ device ref uart0 on end
+ device ref gspi0 on end
+ device ref gspi1 on end
+ device ref pch_espi on end
+ device ref p2sb on end
+ device ref hda on
chip drivers/intel/soundwire
device generic 0 on
chip drivers/soundwire/alc711
@@ -396,10 +361,8 @@
end
end
end
- end # Intel Audio SNDW
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # SPI
- device pci 1f.6 off end # GbE
- device pci 1f.7 off end # TH
+ end
+ device ref smbus on end
+ device ref fast_spi on end
end
end
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 4e4135f..e33eafe 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -153,41 +153,17 @@
}"
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 on end # PEG10
- device pci 02.0 on end # Graphics
- device pci 04.0 on end # DPTF
- device pci 05.0 on end # IPU
- device pci 06.0 on end # PEG60
- device pci 06.2 on end # PEG62
- device pci 07.0 on end # TBT_PCIe0
- device pci 07.1 on end # TBT_PCIe1
- device pci 07.2 off end # TBT_PCIe2
- device pci 07.3 off end # TBT_PCIe3
- device pci 08.0 off end # GNA
- device pci 09.0 off end # NPK
- device pci 0a.0 off end # Crash-log SRAM
- device pci 0d.0 on end # USB xHCI
- device pci 0d.1 off end # USB xDCI (OTG)
- device pci 0d.2 on end # TBT DMA0
- device pci 0d.3 off end # TBT DMA1
- device pci 0e.0 off end # VMD
- device pci 10.0 off end
- device pci 10.1 off end
- device pci 10.6 off end # THC0
- device pci 10.7 off end # THC1
- device pci 11.0 off end
- device pci 11.1 off end
- device pci 11.2 off end
- device pci 11.3 off end
- device pci 11.4 off end
- device pci 11.5 off end
- device pci 12.0 off end # SensorHUB
- device pci 12.5 off end
- device pci 12.6 off end # GSPI2
- device pci 13.0 off end # GSPI3
- device pci 13.1 off end
- device pci 14.0 on
+ device ref pcie5 on end
+ device ref igpu on end
+ device ref dtt on end
+ device ref ipu on end
+ device ref pcie4_0 on end
+ device ref pcie4_1 on end
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp1 on end
+ device ref tcss_xhci on end
+ device ref tcss_dma0 on end
+ device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
@@ -199,49 +175,33 @@
end
end
end
- end # USB3.1 xHCI
- device pci 14.1 off end # USB3.1 xDCI
- device pci 14.2 off end # Shared RAM
- device pci 14.3 on
+ end
+ device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
- end # CNVi: WiFi
- device pci 15.0 on end # I2C0
- device pci 15.1 on end # I2C1
- device pci 15.2 on end # I2C2
- device pci 15.3 on end # I2C3
- device pci 16.0 on end # HECI1
- device pci 16.1 off end # HECI2
- device pci 16.2 off end # CSME
- device pci 16.3 off end # CSME
- device pci 16.4 off end # HECI3
- device pci 16.5 off end # HECI4
- device pci 17.0 on end # SATA
- device pci 19.0 off end # I2C4
- device pci 19.1 on end # I2C5
- device pci 19.2 off end # UART2
- device pci 1c.0 on end # RP1
- device pci 1c.1 off end # RP2
- device pci 1c.2 on end # RP3 # W/A to FSP issue
- device pci 1c.3 on end # RP4 # W/A to FSP issue
- device pci 1c.4 on end # RP5
- device pci 1c.5 on end # RP6
- device pci 1c.6 off end # RP7
- device pci 1c.7 on end # RP8
- device pci 1d.0 on end # RP9
- device pci 1d.1 on end # RP10
- device pci 1d.2 off end # RP11
- device pci 1d.3 off end # RP12
- device pci 1e.0 on end # UART0
- device pci 1e.1 off end # UART1
- device pci 1e.2 on end # GSPI0
- device pci 1e.3 off end # GSPI1
- device pci 1f.0 on end # eSPI
- device pci 1f.1 on end # P2SB
- device pci 1f.2 hidden end # PMC
- device pci 1f.3 on
+ end
+ device ref i2c0 on end
+ device ref i2c1 on end
+ device ref i2c2 on end
+ device ref i2c3 on end
+ device ref heci1 on end
+ device ref sata on end
+ device ref i2c5 on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp8 on end
+ device ref pcie_rp9 on end
+ device ref pcie_rp10 on end
+ device ref uart0 on end
+ device ref gspi0 on end
+ device ref pch_espi on end
+ device ref p2sb on end
+ device ref hda on
chip drivers/intel/soundwire
device generic 0 on
chip drivers/soundwire/alc711
@@ -251,10 +211,8 @@
end
end
end
- end # Intel Audio SNDW
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # SPI
- device pci 1f.6 off end # GbE
- device pci 1f.7 off end # TH
+ end
+ device ref smbus on end
+ device ref fast_spi on end
end
end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
index 68a1bfa..133a737 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb
@@ -1,13 +1,13 @@
chip soc/intel/alderlake
device domain 0 on
- device pci 1f.0 on
+ device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
- end # eSPI
- device pci 1f.2 hidden
+ end
+ device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
@@ -29,6 +29,6 @@
end
end
end
- end # PMC
+ end
end
end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
index 9130a12..bfc8991 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
@@ -1,15 +1,15 @@
chip soc/intel/alderlake
device domain 0 on
- device pci 1f.0 on
+ device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
use conn2 as mux_conn[2]
device pnp 0c09.0 on end
end
- end # eSPI
- device pci 1f.2 hidden
+ end
+ device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
chip drivers/intel/pmc_mux
@@ -37,6 +37,6 @@
end
end
end
- end # PMC
+ end
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Gerrit-Change-Number: 55205
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: newchange
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55204 )
Change subject: cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_CPU_INIT
......................................................................
cpu/x86/lapic: Drop parallel_cpu_init inside LEGACY_CPU_INIT
It was not used, platforms should move away from LEGACY_CPU_INIT
instead of maintaining this.
Change-Id: Id89ec4bb0bdc056ac328f31397e4fab02742e444
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/x86/lapic/lapic_cpu_init.c
1 file changed, 4 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/55204/1
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 1c1c15d..ab38025 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -20,8 +20,6 @@
#include <stdlib.h>
#include <thread.h>
-const int parallel_cpu_init = false;
-
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -289,8 +287,7 @@
{
atomic_inc(&active_cpus);
- if (!parallel_cpu_init)
- spin_lock(&start_cpu_lock);
+ spin_lock(&start_cpu_lock);
#ifdef __SSE3__
/*
@@ -304,8 +301,7 @@
#endif
cpu_initialize(index);
- if (!parallel_cpu_init)
- spin_unlock(&start_cpu_lock);
+ spin_unlock(&start_cpu_lock);
atomic_dec(&active_cpus);
@@ -321,9 +317,6 @@
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
- if (parallel_cpu_init && (cpu == bsp_cpu))
- continue;
-
if (!cpu->enabled)
continue;
@@ -335,8 +328,7 @@
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
- if (!parallel_cpu_init)
- udelay(10);
+ udelay(10);
}
}
@@ -439,14 +431,10 @@
if (!CONFIG(SERIALIZED_SMM_INITIALIZATION))
smm_init();
- /* start all aps at first, so we can init ECC all together */
- if (is_smp_boot() && parallel_cpu_init)
- start_other_cpus(cpu_bus, info->cpu);
-
/* Initialize the bootstrap processor */
cpu_initialize(0);
- if (is_smp_boot() && !parallel_cpu_init)
+ if (is_smp_boot())
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id89ec4bb0bdc056ac328f31397e4fab02742e444
Gerrit-Change-Number: 55204
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newchange
Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55203 )
Change subject: cpu/x86: Drop Kconfig PARALLEL_CPU_INIT
......................................................................
cpu/x86: Drop Kconfig PARALLEL_CPU_INIT
Change-Id: Ibe2c24228045cbf1ed2a6b0cb0a67848cbf03019
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/cpu/intel/hyperthreading/intel_sibling.c
M src/cpu/x86/Kconfig
M src/cpu/x86/lapic/lapic_cpu_init.c
3 files changed, 9 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55203/1
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index 38f6efc..93d29d4 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -6,9 +6,7 @@
#include <option.h>
#include <smp/spinlock.h>
-#if CONFIG(PARALLEL_CPU_INIT)
-#error Intel hyper-threading requires serialized CPU init
-#endif
+/* Intel hyper-threading requires serialized CPU init. */
static int first_time = 1;
static int disable_siblings = !CONFIG(LOGICAL_CPUS);
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c769865..de5535f 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -1,8 +1,3 @@
-# TODO These two options look too similar
-config PARALLEL_CPU_INIT
- bool
- default n
-
config PARALLEL_MP
def_bool y
depends on !LEGACY_CPU_INIT
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fe1c824..1c1c15d 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -20,6 +20,8 @@
#include <stdlib.h>
#include <thread.h>
+const int parallel_cpu_init = false;
+
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -287,7 +289,7 @@
{
atomic_inc(&active_cpus);
- if (!CONFIG(PARALLEL_CPU_INIT))
+ if (!parallel_cpu_init)
spin_lock(&start_cpu_lock);
#ifdef __SSE3__
@@ -302,7 +304,7 @@
#endif
cpu_initialize(index);
- if (!CONFIG(PARALLEL_CPU_INIT))
+ if (!parallel_cpu_init)
spin_unlock(&start_cpu_lock);
atomic_dec(&active_cpus);
@@ -319,7 +321,7 @@
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
- if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
+ if (parallel_cpu_init && (cpu == bsp_cpu))
continue;
if (!cpu->enabled)
@@ -333,7 +335,7 @@
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
- if (!CONFIG(PARALLEL_CPU_INIT))
+ if (!parallel_cpu_init)
udelay(10);
}
@@ -438,13 +440,13 @@
smm_init();
/* start all aps at first, so we can init ECC all together */
- if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT))
+ if (is_smp_boot() && parallel_cpu_init)
start_other_cpus(cpu_bus, info->cpu);
/* Initialize the bootstrap processor */
cpu_initialize(0);
- if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT))
+ if (is_smp_boot() && !parallel_cpu_init)
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
--
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Gerrit-Change-Id: Ibe2c24228045cbf1ed2a6b0cb0a67848cbf03019
Gerrit-Change-Number: 55203
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange