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Hello Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/55213
to review the following change.
Change subject: cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
......................................................................
cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
The MSR only needs to be set when IO MWAIT redirection is to be enabled.
Change-Id: Ie856086babe4dadc690f701bd90a7bbac88cb4ad
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/cpu/intel/model_206ax/model_206ax_init.c
1 file changed, 0 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/55213/1
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index beb885e..7a40644 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -172,12 +172,6 @@
msr.lo |= (1 << 15); // Lock C-State MSR
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
- msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
- msr.lo &= ~0x7ffff;
- msr.lo |= (PMB0_BASE + 4); // LVL_2 base address
- msr.lo |= (2 << 16); // CST Range: C7 is max C-state
- wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
-
msr = rdmsr(MSR_MISC_PWR_MGMT);
msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
wrmsr(MSR_MISC_PWR_MGMT, msr);
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54901 )
Change subject: amdfwtool: Add a function to extract firmwares
......................................................................
Patch Set 14:
(1 comment)
File util/amdfwtool/extract.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120736):
https://review.coreboot.org/c/coreboot/+/54901/comment/f7691c28_23d70c78
PS14, Line 91: close (mod_fd);
space prohibited between function name and open parenthesis '('
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55205 )
Change subject: mb/intel/adlrvp: Use device aliases
......................................................................
Patch Set 3:
(6 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55205/comment/4f1efbc1_b73e106d
PS2, Line 320: device pci 10.0 off end
: device pci 10.1 off end
: device pci 10.6 off end # THC0
: device pci 10.7 off end # THC1
> Below devices are THC0 and 1 for ADL-P […]
Hmmm, I see. It's somewhat annoying (why couldn't ADL-P and ADL-S use the same PCI B:D.F for these devices?) but we'll have to live with it. Maybe we will end up using two separate chipset devicetrees for ADL-P and ADL-S.
https://review.coreboot.org/c/coreboot/+/55205/comment/4b9f1961_00cccfd3
PS2, Line 324: device pci 11.0 off end
: device pci 11.1 off end
: device pci 11.2 off end
: device pci 11.3 off end
: device pci 11.4 off end
: device pci 11.5 off end
> same these devices belongs to ADL-S
Alright, I see. I'd appreciate if you could remove ADL-S devices in a separate commit.
https://review.coreboot.org/c/coreboot/+/55205/comment/b247ee02_7a786431
PS2, Line 331: device pci 12.5 off end
> I don't see this device, mostly some mistake, better to remove this device from list
I'd remove it in the same commit that removes the ADL-S devices (see comment above), and mention why in that commit's message.
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55205/comment/c073d70f_853abd66
PS3, Line 372: # W/A to FSP issue
Does this comment still apply?
File src/mainboard/intel/adlrvp/devicetree_m.cb:
https://review.coreboot.org/c/coreboot/+/55205/comment/c6a09818_89740b8a
PS3, Line 202: device ref pch_espi on end
Already on in chipset.cb
https://review.coreboot.org/c/coreboot/+/55205/comment/38cbd357_ff97b73e
PS3, Line 216: device ref fast_spi on end
Already on in chipset.cb
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55209 )
Change subject: soc/intel/alderlake: Add IDE-R and KT device into chipset.cb
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55209/comment/16adc908_3cfe7866
PS1, Line 9: Add IDE-R and KT device to chipset.cb and leave it off by default.
> I don't have a datasheet, are these devices still IDE-R and KT in Alder Lake?
Yes they are.
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55206
to look at the new patch set (#2).
Change subject: mb/intel/sm: Use device aliases
......................................................................
mb/intel/sm: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
1 file changed, 41 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/55206/2
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