coreboot-gerrit June 2021

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Change in coreboot[master]: sb/intel/ibexpeak: Drop P_LVLx support in FADT
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Stefan Ott, Nico Huber, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Hello Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55217 to review the following change. Change subject: sb/intel/ibexpeak: Drop P_LVLx support in FADT ...................................................................... sb/intel/ibexpeak: Drop P_LVLx support in FADT IO MWAIT redirection is not enabled. The code is missing, but C-states should instead be reported using the _CST ACPI object. Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/southbridge/intel/ibexpeak/fadt.c 3 files changed, 3 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/55217/1 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 5f167df..28604cc 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -49,7 +49,6 @@ register "gen3_dec" = "0x1c1681" # EC ? register "gen4_dec" = "0x040069" # ? - register "c2_latency" = "1" register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index e142a1c..effe4ef 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -49,7 +49,6 @@ register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "c2_latency" = "1" register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index ccd9f57..40c8bdc 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -11,7 +11,6 @@ struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; fadt->sci_int = 0x9; @@ -32,12 +31,9 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; + /* P_LVLx not used */ + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; @@ -54,9 +50,6 @@ if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; -- To view, visit https://review.coreboot.org/c/coreboot/+/55217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21fd2fa6ee4aa1ed57694549d5cb48159f37af26 Gerrit-Change-Number: 55217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/intel/model_206ax/acpi.c: Do not report P_BLK
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

1 0

Change in coreboot[master]: cpu/intel/model_206ax/acpi.c: Do not report P_BLK
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

1 0

Change in coreboot[master]: cpu/intel/haswell/acpi.c: Do not report P_BLK
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

1 0

Change in coreboot[master]: cpu/intel/model_206ax: Do not set PMG_IO_CAPTURE_ADDR MSR
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

1 0

Change in coreboot[master]: bd82x6x boards: Drop redundant `c2_latency`
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph. Hello Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55212 to review the following change. Change subject: bd82x6x boards: Drop redundant `c2_latency` ...................................................................... bd82x6x boards: Drop redundant `c2_latency` If unspecified, chipset code already uses 101, and 0x65 == 101. Change-Id: I524ca492fa577003df23017756f74a455582132f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8z77-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/optiplex_9010/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb 31 files changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/55212/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 3689926..8f7573a 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -25,7 +25,6 @@ device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index eb0c944..83b6597 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -33,7 +33,6 @@ subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index 07c0a86..32f0cd4 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 5860556..ca09d2f 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -19,7 +19,6 @@ device pci 02.0 on end # VGA controller chip southbridge/intel/bd82x6x - register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asus/p8z77-series/devicetree.cb b/src/mainboard/asus/p8z77-series/devicetree.cb index 1b9d14d..9710118 100644 --- a/src/mainboard/asus/p8z77-series/devicetree.cb +++ b/src/mainboard/asus/p8z77-series/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 9dc6a7c..35c3ae3 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -18,7 +18,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x003c0a01" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 536eef7..b3b1a1c 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -31,7 +31,6 @@ subsystemid 0x8086 0x7270 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x0000164d" register "gen2_dec" = "0x000c0681" diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb index c85f2e4..ec585b9 100644 --- a/src/mainboard/dell/optiplex_9010/devicetree.cb +++ b/src/mainboard/dell/optiplex_9010/devicetree.cb @@ -24,7 +24,6 @@ register "alt_gp_smi_en" = "0x0004" register "gpi2_routing" = "1" register "gpi12_routing" = "2" - register "c2_latency" = "0x0065" register "gen1_dec" = "0x007c0a01" register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 8816f10..7ca9a8b 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -31,7 +31,6 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "c2_latency" = "0x0065" device pci 14.0 on # USB 3.0 Controller subsystemid 0x1458 0x5007 diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 479d813..3f07202 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -18,7 +18,6 @@ device pci 02.0 on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x003c0a01" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 7cdb8a3..9dee30f 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -60,8 +60,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 0d83267..76d04d6 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -24,7 +24,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 7fc936d..3dd8825 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -29,7 +29,6 @@ device pci 00.0 on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH - register "c2_latency" = "0x0065" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 0aca0a6..5204e60 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -24,7 +24,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 7 PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index c554b6c..389b44e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -28,7 +28,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "sata_port_map" = "0x1" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 950d68a..a878019 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -34,8 +34,6 @@ # Disable root port coalescing register "pcie_port_coalesce" = "0" - register "c2_latency" = "101" # c2 not supported - register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 4655baa..86205f8 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -30,7 +30,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x007c1611" register "gen2_dec" = "0x00040069" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index fbf54d4..3c1fc9e 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -28,7 +28,6 @@ device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x00000000" register "gen2_dec" = "0x000c0701" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 3ba3a2d..e42e519 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -57,8 +57,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index cfe8929..ab98ca0 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -59,8 +59,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 950e83d..112dfe7 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -28,7 +28,6 @@ subsystemid 0x17aa 0x21f3 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x000c15e1" register "gen2_dec" = "0x007c1601" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 7f95170..75a65f9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -59,7 +59,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 40b005d..a1e24d5 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -57,8 +57,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b179f4f..ffa0b93 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -53,7 +53,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index dc9e037..abe40b1 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -56,7 +56,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "0x0065" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 2707197..30260b0 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -58,7 +58,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index a41cfea..53eb23a 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -57,8 +57,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a774d84..1f81311 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -59,7 +59,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 083c427..6c97e1f 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 35c77aa..876f920 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -12,7 +12,6 @@ end device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" register "pcie_port_coalesce" = "1" diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 13b2043..49fcff5 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -16,7 +16,6 @@ device pci 02.0 off end # iGPU device pci 06.0 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) -- To view, visit https://review.coreboot.org/c/coreboot/+/55212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I524ca492fa577003df23017756f74a455582132f Gerrit-Change-Number: 55212 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]amdfwtool: Add a script to replace AMD firmware
by build bot (Jenkins) (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Zheng Bao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55160 ) Change subject: [WIP]amdfwtool: Add a script to replace AMD firmware ...................................................................... Patch Set 4: (4 comments) File util/amdfwtool/replace.sh: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120737): https://review.coreboot.org/c/coreboot/+/55160/comment/f0decaed_70aeec1a PS4, Line 12: CBFS_ADDRESS=$(eval $CBFSTOOL $IMAGE layout | grep "^'COREBOOT'" | sed "s/'COREBOOT' (CBFS, size [0-9]\+, offset $[0-9]\+$)/\1/g") line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120737): https://review.coreboot.org/c/coreboot/+/55160/comment/5a1e18d9_789414a5 PS4, Line 15: AMDFW_ADDRESS=0x$(eval printf %x $(eval expr 4294967295 + 1 - $(($ROMSIZE)) + $CBFS_ADDRESS + $AMDFW_OFFSET + 64)) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120737): https://review.coreboot.org/c/coreboot/+/55160/comment/2fbc294b_6db87c55 PS4, Line 72: --instance 0 --apcb BiosDirL20_Typex60.bin --instance 10 --apcb BiosDirL20_Typex68.bin --apob-base 0x2001000 --bios-bin $BIOS_BIN_FILE --bios-bin-dest $BIOS_BIN_DEST --bios-uncomp-size $BIOS_BIN_SIZE --soft-fuse $SOFT_FUSE --use-pspsecureos --load-s0i3 --combo-capable "--token-unlock" --spi-read-mode 2 --spi-speed 0 --spi-micron-flag 0 --config "fw.cfg" --soc-name "Cezanne" --flashsize $ROMSIZE \ line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120737): https://review.coreboot.org/c/coreboot/+/55160/comment/62a49693_5956fccf PS4, Line 84: $CBFSTOOL $IMAGE_NEW add -f amdfw_n.rom -n apu/amdfw -t raw -r COREBOOT -b $(($AMDFW_ADDRESS)) line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib450277d55ad254234a451e06747121fff731ee0 Gerrit-Change-Number: 55160 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 04 Jun 2021 11:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Add a function to extract firmwares
by build bot (Jenkins) (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54901 ) Change subject: amdfwtool: Add a function to extract firmwares ...................................................................... Patch Set 14: (1 comment) File util/amdfwtool/extract.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120736): https://review.coreboot.org/c/coreboot/+/54901/comment/f7691c28_23d70c78 PS14, Line 91: close (mod_fd); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/54901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a6c7ff56cc11530695d1068763ecdd86282a17 Gerrit-Change-Number: 54901 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 11:10:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Use relative address for EFS gen2
by Bao Zheng (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55211 to review the following change. Change subject: amdfwtool: Use relative address for EFS gen2 ...................................................................... amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can also run with phycical address, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/55211/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 825dea6..feefeac 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -343,11 +343,12 @@ typedef struct _context { char *rom; /* target buffer, size of flash device */ uint32_t rom_size; /* size of flash device */ + uint32_t abs_address; uint32_t current; /* pointer within flash & proxy buffer */ } context; #define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) -#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) +#define RUN_OFFSET(ctx, offset) ((ctx).abs_address ? RUN_BASE(ctx) + (offset) : (offset)) #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset))) #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current) @@ -1533,8 +1534,6 @@ romsig_offset = ctx.current = dir_location - rom_base_address; else romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; - printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", - RUN_CURRENT(ctx)); amd_romsig = BUFF_OFFSET(ctx, romsig_offset); amd_romsig->signature = EMBEDDED_FW_SIGNATURE; @@ -1545,6 +1544,10 @@ if (soc_id != PLATFORM_UNKNOWN) { retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); + if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN) + ctx.abs_address = 0; + else + ctx.abs_address = 1; if (retval) { fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); return retval; @@ -1553,6 +1556,9 @@ fprintf(stderr, "WARNING: No SOC name specified.\n"); } + printf(" AMDFWTOOL Using firmware directory location of 0x%08x\n", + RUN_CURRENT(ctx)); + integrate_firmwares(&ctx, amd_romsig, amd_fw_table); ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Gerrit-Change-Number: 55211 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add IDE-R and KT device into chipset.cb
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55209 ) Change subject: soc/intel/alderlake: Add IDE-R and KT device into chipset.cb ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55209/comment/dd8a17ab_d35c9c7d PS1, Line 9: Add IDE-R and KT device to chipset.cb and leave it off by default. > Yes they are. Alright, thanks for confirming! -- To view, visit https://review.coreboot.org/c/coreboot/+/55209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98 Gerrit-Change-Number: 55209 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 10:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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