coreboot-gerrit June 2021

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Change in coreboot[master]: amdfwtool: Use relative address for EFS gen2
by Bao Zheng (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55211 to look at the new patch set (#2). Change subject: amdfwtool: Use relative address for EFS gen2 ...................................................................... amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can also run with phycical address, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/55211/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Gerrit-Change-Number: 55211 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55221 ) Change subject: mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Gerrit-Change-Number: 55221 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 11:24:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTME] drivers/pc80/rtc/option.c: Allow integer options to cross by...
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52647 to look at the new patch set (#7). Change subject: [TESTME] drivers/pc80/rtc/option.c: Allow integer options to cross byte boundaries ...................................................................... [TESTME] drivers/pc80/rtc/option.c: Allow integer options to cross byte boundaries Redesign CMOS option handling code to allow accessing integer options whose bit offset crosses byte boundaries. This allows cramming more CMOS settings in the same space without having to play Tetris. The new system is most likely not backwards-compatible for options that cross byte boundaries (it was not meant to be backwards-compatible). However, this is a non-issue, as all CMOS options used in coreboot never cross byte boundaries. Change-Id: Id1e0ed05efeaaa999223bd209f977a096fa39e15 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/pc80/rtc/option.c 1 file changed, 64 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52647/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e0ed05efeaaa999223bd209f977a096fa39e15 Gerrit-Change-Number: 52647 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/sm: Use device aliases
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55206 to look at the new patch set (#3). Change subject: mb/intel/sm: Use device aliases ...................................................................... mb/intel/sm: Use device aliases Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all shadowmountain board variants. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 41 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/55206/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912 Gerrit-Change-Number: 55206 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Use device aliases
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55205 to look at the new patch set (#4). Change subject: mb/intel/adlrvp: Use device aliases ...................................................................... mb/intel/adlrvp: Use device aliases Use the device aliases provided by alderlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all different adlrvp boards. TEST=Dump devicetree device enable list without and with this CL, no difference observed. Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb 4 files changed, 88 insertions(+), 151 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/55205/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Gerrit-Change-Number: 55205 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Use device aliases
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55205 ) Change subject: mb/intel/adlrvp: Use device aliases ...................................................................... Patch Set 3: (7 comments) File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55205/comment/b04a1065_0222a53c PS2, Line 320: device pci 10.0 off end : device pci 10.1 off end : device pci 10.6 off end # THC0 : device pci 10.7 off end # THC1 > Hmmm, I see. It's somewhat annoying (why couldn't ADL-P and ADL-S use the same PCI B:D. […] true https://review.coreboot.org/c/coreboot/+/55205/comment/9628e877_c4e5afb6 PS2, Line 324: device pci 11.0 off end : device pci 11.1 off end : device pci 11.2 off end : device pci 11.3 off end : device pci 11.4 off end : device pci 11.5 off end > Alright, I see. I'd appreciate if you could remove ADL-S devices in a separate commit. CB:55221 Ack https://review.coreboot.org/c/coreboot/+/55205/comment/9498bd56_ae98a4ce PS2, Line 331: device pci 12.5 off end > I'd remove it in the same commit that removes the ADL-S devices (see comment above), and mention why […] CB:55221 Ack https://review.coreboot.org/c/coreboot/+/55205/comment/769e433c_51b2909f PS2, Line 334: device pci 13.1 off end > Its for ADL-S Ack File src/mainboard/intel/adlrvp/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55205/comment/49117629_adf98c19 PS3, Line 372: # W/A to FSP issue > Does this comment still apply? good point, let me keep those as is, till the time i have verify with latest FSP File src/mainboard/intel/adlrvp/devicetree_m.cb: https://review.coreboot.org/c/coreboot/+/55205/comment/c1bb0d3d_34b5ea4c PS3, Line 202: device ref pch_espi on end > Already on in chipset. […] Ack https://review.coreboot.org/c/coreboot/+/55205/comment/34005b2f_aca466ce PS3, Line 216: device ref fast_spi on end > Already on in chipset. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5 Gerrit-Change-Number: 55205 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 11:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55221 ) Change subject: mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb ...................................................................... mb/intel/{adlrvp, sm}: Remove ADL-S devices from ADL-P/M devicetree.cb Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 3 files changed, 0 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/55221/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 23913cc..04c3272 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -319,19 +319,9 @@ device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end device pci 12.0 off end # SensorHUB - device pci 12.5 off end device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3 - device pci 13.1 off end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4e4135f..4ebfff2 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -174,19 +174,9 @@ device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end device pci 12.0 off end # SensorHUB - device pci 12.5 off end device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3 - device pci 13.1 off end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 43a23a1..52b35fa 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -200,19 +200,9 @@ device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end device pci 12.0 off end # SensorHUB - device pci 12.5 off end device pci 12.6 off end # GSPI2 device pci 13.0 off end # GSPI3 - device pci 13.1 off end device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/55221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I095394d9a79506346b8464c850d03cbd8ce2b812 Gerrit-Change-Number: 55221 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch: Drop P_LVLx support in FADT
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

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Change in coreboot[master]: sb/intel/lynxpoint: Drop P_LVLx support in FADT
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

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Change in coreboot[master]: sb/intel/bd82x6x: Drop P_LVLx support in FADT
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Nico Huber, Arthur Heymans, Patrick Rudolph. Hello Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55218 to review the following change. Change subject: sb/intel/bd82x6x: Drop P_LVLx support in FADT ...................................................................... sb/intel/bd82x6x: Drop P_LVLx support in FADT IO MWAIT redirection is not enabled, and C-states are reported using the _CST ACPI object, which overrides the P_LVLx values. Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/fadt.c M util/autoport/bd82x6x.go 9 files changed, 3 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/55218/1 diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 33ef305..fda74da 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -58,8 +58,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "1" - device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index dbbb5cd..d748277 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -56,8 +56,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "1" - device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1ec596e..d1d39e5 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -63,8 +63,6 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "1" - device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 80ae789..170dbaa 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -45,8 +45,6 @@ # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" - register "c2_latency" = "1" - device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 85d140c..716d1b8 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -56,8 +56,6 @@ register "gen2_dec" = "0x003c0b01" register "gen3_dec" = "0x00fc1601" - register "c2_latency" = "1" - device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 6ee21af..90ed429 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -38,8 +38,6 @@ register "sata_port_map" = "0x3" - register "c2_latency" = "1" - register "gen1_dec" = "0x00fc1601" # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 45f1226..6ef18fd 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -70,7 +70,6 @@ uint8_t pcie_aspm_f6; uint8_t pcie_aspm_f7; - int c2_latency; int docking_supported; uint8_t pcie_hotplug_map[8]; diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index b0f4777..77af4e8 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -11,7 +11,6 @@ struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - int c2_latency; fadt->sci_int = 0x9; @@ -32,12 +31,9 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - c2_latency = chip->c2_latency; - if (!c2_latency) { - c2_latency = 101; /* c2 unsupported */ - } - fadt->p_lvl2_lat = c2_latency; - fadt->p_lvl3_lat = 87; + /* P_LVLx not used */ + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; @@ -55,9 +51,6 @@ if (chip->docking_supported) { fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } - if (c2_latency < 100) { - fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED; - } fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index e2a84e4..ad8918a 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -230,7 +230,6 @@ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), - "c2_latency": FormatHexLE16(FADT[96:98]), "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), -- To view, visit https://review.coreboot.org/c/coreboot/+/55218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8 Gerrit-Change-Number: 55218 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit June 2021