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Change subject: Documentation: Add proposal to allow enabling serial console with a flag
......................................................................
Documentation: Add proposal to allow enabling serial console with a flag
BUG=b:172341184, b:151780766
Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
A Documentation/technotes/2021-05-selectable-serial-console.md
M Documentation/technotes/index.md
2 files changed, 136 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/54385/4
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
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Change subject: mb/intel/sm: Use device aliases
......................................................................
mb/intel/sm: Use device aliases
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
1 file changed, 41 insertions(+), 73 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/55206/4
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55206 )
Change subject: mb/intel/sm: Use device aliases
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Patchset:
PS3:
Other than one thing, looks good. I'd like to have others take a look as well.
File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/55206/comment/a34e7d7f_416900f2
PS3, Line 180: ipu
pcie4_0
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Change subject: mb/intel/adlrvp: Use device aliases
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
Looks good, but I'll let others take a look as well. I may have missed something.
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Attention is currently required from: Zheng Bao.
Hello Zheng Bao,
I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Use relative address for EFS gen2
......................................................................
amdfwtool: Use relative address for EFS gen2
The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.
Chips like Cezanne can also run with phycical address,
so no problem comes up so far.
BUG=b:188754219
Test=Majolica (Cezanne)
Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 9 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/55211/2
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Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans.
Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: [TESTME] drivers/pc80/rtc/option.c: Allow integer options to cross byte boundaries
......................................................................
[TESTME] drivers/pc80/rtc/option.c: Allow integer options to cross byte boundaries
Redesign CMOS option handling code to allow accessing integer options
whose bit offset crosses byte boundaries. This allows cramming more CMOS
settings in the same space without having to play Tetris.
The new system is most likely not backwards-compatible for options that
cross byte boundaries (it was not meant to be backwards-compatible).
However, this is a non-issue, as all CMOS options used in coreboot never
cross byte boundaries.
Change-Id: Id1e0ed05efeaaa999223bd209f977a096fa39e15
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/drivers/pc80/rtc/option.c
1 file changed, 64 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52647/7
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