coreboot-gerrit June 2021

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55224/comment/e5640a73_dd5b95ab PS1, Line 15: Also, as an example, transform hp/280_g2 to make use of this code. nit: Probably mention that the Kconfig can be dropped once all relevant boards are updated to select this new Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:57:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01
by Ronak Kanabar (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Tim Wawrzynczak, Srinidhi N Kaushik, Patrick Rudolph. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55094 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01 ...................................................................... Patch Set 3: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h: https://review.coreboot.org/c/coreboot/+/55094/comment/a9da1d71_5772ebeb PS3, Line 1252: Reserved19 > UsbTcPortEn needs to be exposed to enable TCSS ports. will check and revise the patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/55094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Gerrit-Change-Number: 55094 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:51:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01
by Sridhar Siricilla (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Tim Wawrzynczak, Srinidhi N Kaushik, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55094 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01 ...................................................................... Patch Set 3: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h: https://review.coreboot.org/c/coreboot/+/55094/comment/1eceda9d_f0da861f PS3, Line 1252: Reserved19 UsbTcPortEn needs to be exposed to enable TCSS ports. -- To view, visit https://review.coreboot.org/c/coreboot/+/55094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Gerrit-Change-Number: 55094 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/55224/comment/f9544856_1c8ac450 PS1, Line 180: DERIVE_SERIALIO_CFG_FROM_DEV_STATE > It's necessary for now, but can be removed once all mainboards select it. Having it allows adapting each board in a separate commit, which is useful because some boards may have inconsistencies (between SerialIoDevMode values and device states). Makes sense. I was suspecting the same. Thanks for confirming! -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/55224/comment/9f839272_4d20e41c PS1, Line 180: DERIVE_SERIALIO_CFG_FROM_DEV_STATE > Is this Kconfig required? It's necessary for now, but can be removed once all mainboards select it. Having it allows adapting each board in a separate commit, which is useful because some boards may have inconsistencies (between SerialIoDevMode values and device states). > The change looks like the direction we would want to go in for all mainboards i.e. eliminate the devicetree config and instead rely on SoC determining the correct values for the UPDs based on device state in devicetree and other configs. I fully agree. https://review.coreboot.org/c/coreboot/+/55224/comment/b7a254c9_3f34c351 PS1, Line 186: When enabled, the `SerialIoDevMode` setting in chip config is useless. > It’d make it the other way around `EXPLICIT_SERIALIO_CFG`, so boards needing this have to select it. Usually, I would agree. However, doing so in this commit means that all boards except hp/280_g2 would have to select `EXPLICIT_SERIALIO_CFG`, which would be rather noisy. Plus, if we're going to update all mainboards to not use `SerialIoDevMode` in the devicetree (see Furquan's comment), we will end up removing the Kconfig option altogether. -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:34:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86: Default to PARALLEL_MP selected
by Arthur Heymans (Code Review) 04 Jun '21

04 Jun '21

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Change in coreboot[master]: cpu/x86: Default to PARALLEL_MP selected
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Damien Zammit, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Hello build bot (Jenkins), Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Damien Zammit, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55196 to look at the new patch set (#3). Change subject: cpu/x86: Default to PARALLEL_MP selected ...................................................................... cpu/x86: Default to PARALLEL_MP selected Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig M src/northbridge/amd/pi/00730F01/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/example/min86/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 33 files changed, 19 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55196/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Gerrit-Change-Number: 55196 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Nice idea. File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/55224/comment/1a9f3faf_4f3a3421 PS1, Line 186: When enabled, the `SerialIoDevMode` setting in chip config is useless. It’d make it the other way around `EXPLICIT_SERIALIO_CFG`, so boards needing this have to select it. -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Drop unused lpss functions
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55226 ) Change subject: soc/intel: Drop unused lpss functions ...................................................................... soc/intel: Drop unused lpss functions This change drops the following unused lpss functions and related code: * soc_lpss_controllers_list * is_dev_lpss These functions were added to determine if a controller is LPSS for performing IRQ configuration. But, these never got used and hence are being dropped. Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 8 files changed, 0 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/55226/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8664fe6..22329f2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -67,22 +67,6 @@ params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_GSPI3, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) { /* Override settings per board. */ @@ -334,10 +318,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d7772f1..5ac51f0 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -19,21 +19,6 @@ #include "chip.h" -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - /* * Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP * UPD expected value for Serial IO since valid enum index starts from 1. @@ -572,13 +557,6 @@ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} - /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 8d22e7a..5cfd5c5 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -27,13 +27,4 @@ /* Set controller power state to D0 or D3*/ void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); -/* - * Handler to get list of LPSS controllers. The SOC is expected to send out a - * list of pci devfn for all LPSS controllers supported by the SOC. - */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size); - -/* Check if the device is a LPSS controller */ -bool is_dev_lpss(const struct device *dev); - #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 6e33c0f..70a5934 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -72,21 +72,3 @@ reg8 |= state; pci_s_write_config8(devfn, PME_CTRL_STATUS, reg8); } - -bool is_dev_lpss(const struct device *dev) -{ - static size_t size; - static const pci_devfn_t *lpss_devices; - - if (dev->path.type != DEVICE_PATH_PCI) - return false; - - if (!lpss_devices) - lpss_devices = soc_lpss_controllers_list(&size); - - for (int i = 0; i < size; i++) { - if (lpss_devices[i] == dev->path.pci.devfn) - return true; - } - return false; -} diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index f02d20e..611d12b 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -41,23 +41,6 @@ return ctl - 1; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_I2C6, - PCH_DEVFN_I2C7, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_elkhartlake_config *config = config_of_soc(); @@ -287,10 +270,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 184b9d6..395bca8 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -33,21 +33,6 @@ params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -223,10 +208,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index eefbf6c..dcee306 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -28,21 +28,6 @@ EOP_DXE, } EndOfPost; -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_jasperlake_config *config = config_of_soc(); @@ -266,10 +251,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 7c9ab88..616daa0 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -132,22 +132,6 @@ params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; } -static const pci_devfn_t serial_io_dev[] = { - PCH_DEVFN_I2C0, - PCH_DEVFN_I2C1, - PCH_DEVFN_I2C2, - PCH_DEVFN_I2C3, - PCH_DEVFN_I2C4, - PCH_DEVFN_I2C5, - PCH_DEVFN_GSPI0, - PCH_DEVFN_GSPI1, - PCH_DEVFN_GSPI2, - PCH_DEVFN_GSPI3, - PCH_DEVFN_UART0, - PCH_DEVFN_UART1, - PCH_DEVFN_UART2 -}; - __weak void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) { /* Override settings per board. */ @@ -483,10 +467,3 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } - -/* Return list of SOC LPSS controllers */ -const pci_devfn_t *soc_lpss_controllers_list(size_t *size) -{ - *size = ARRAY_SIZE(serial_io_dev); - return serial_io_dev; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/55226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Gerrit-Change-Number: 55226 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add proposal to allow enabling serial console with a flag
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Paul Menzel, Stefan Reinauer, Julius Werner, Arthur Heymans. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54385 ) Change subject: Documentation: Add proposal to allow enabling serial console with a flag ...................................................................... Patch Set 4: (1 comment) File Documentation/technotes/2021-05-selectable-serial-console.md: https://review.coreboot.org/c/coreboot/+/54385/comment/58ed27c0_c17b8ffd PS4, Line 127: To avoid adding complexity in the bootblock, bootblock is exempt from : this: When enabling this mode, bootblock stage code will not send data : to serial for performance reason > Yes. […] No, I think this is fine. I was slightly confused by the statement: "When enabling this mode, bootblock stage will not send data to serial for performance reason". I wanted to make sure mode here meant the Kconfig being selected. Read this section again and it makes sense to me now. Thanks for confirming! -- To view, visit https://review.coreboot.org/c/coreboot/+/54385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1b0efc55880095f9d5d6d6e448f2c8677d57ff5 Gerrit-Change-Number: 54385 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Jun 2021 13:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2021