coreboot-gerrit June 2021

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55225 ) Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55225/comment/48f15146_d48539b5 PS1, Line 320: /* Fill IGD related FSP-M UPDs */ : fill_igd_memory_init_params(m_cfg, config); : : /* Fill Memory related FSP-M UPDs */ : fill_memory_memory_init_params(m_cfg, config); : : /* Fill CPU related FSP-M UPDs */ : fill_cpu_memory_init_params(m_cfg, config); : : /* Fill security related FSP-M UPDs */ : fill_security_memory_init_params(m_cfg); : : /* Fill UART debug related FSP-M UPDs */ : fill_uart_memory_init_params(m_cfg); : : /* Fill IPU related FSP-M UPDs */ : fill_ipu_memory_init_params(m_cfg); : : /* Fill SMBUS related FSP-M UPDs */ : fill_smbus_memory_init_params(m_cfg); : : /* Fill Miscellaneous FSP-M UPDs */ : fill_misc_memory_init_params(m_cfg, config); : : /* Fill Audio related FSP-M UPDs */ : fill_audio_memory_init_params(m_cfg, config); : : /* Fill PCIE related RP FSP-M UPDs */ : fill_pcie_rp_memory_init_params(m_cfg, config); : : /* Fill ISH related FSP-M UPD */ : fill_ish_memory_init_params(m_cfg); : : /* Fill TCSS related FSP-M UPD */ : fill_tcss_memory_init_params(m_cfg); : : /* Fill USB4/TBT related FSP-M UPD */ : fill_usb4_memory_init_params(m_cfg); : : /* Fill VT-d related FSP-M UPD */ : fill_vtd_memory_init_params(m_cfg); : : /* Fill trace related FSP-M UPD */ : fill_trace_memory_init_params(m_cfg); > I don't think we need a comment on every function call. […] Thanks Angel for awesome feedback, i will adhere to this and it make sense to me as well -- To view, visit https://review.coreboot.org/c/coreboot/+/55225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Gerrit-Change-Number: 55225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 14:20:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55225 ) Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55225/comment/d0b204bb_63624548 PS1, Line 12: This would help to increase the code readability and in future : meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly I like this change! :). File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55225/comment/ccbbea9d_da538af4 PS1, Line 63: memory_init nit: Since all these functions live within romstage/fsp_params.c, do we need memory_init in the name here? Just `fill_xyz_params()` or `fill_fspm_xyz_params()`? https://review.coreboot.org/c/coreboot/+/55225/comment/adee9629_cc4f95c7 PS1, Line 72: Probably as part of follow-up change, this can be updated to set UPDs differently based on InternalGfx: ``` if (m_cfg->InternalGfx) { m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig; ... } else { m_cfg->IgdDvmt50PreAlloc = 0; m_cfg->DdiPortAConfig = 0; m_cfg->DdiPortBConfig = 0; ... } ``` https://review.coreboot.org/c/coreboot/+/55225/comment/c29e81f2_bc78aae1 PS1, Line 101: m_cfg->ChHashMask = 0x30CC; Not for this change, but this setting doesn't even take effect. ChHashOverride is set to 0. I think this should be dropped in a follow-up CL. https://review.coreboot.org/c/coreboot/+/55225/comment/bcf5a5a3_06a0ae45 PS1, Line 187: disable This function is not just disabling clksrc. https://review.coreboot.org/c/coreboot/+/55225/comment/216c2458_c386e190 PS1, Line 320: Fill IGD related FSP-M UPDs nit: Not sure if the comments are really required since they mostly repeat the function names. If you think it is good to have them, feel free to leave as is. -- To view, visit https://review.coreboot.org/c/coreboot/+/55225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Gerrit-Change-Number: 55225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 14:18:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by build bot (Jenkins) (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath, Deepti Deshatty. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/romstage_fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120772): https://review.coreboot.org/c/coreboot/+/50996/comment/c7e8e9f0_63088e9a PS7, Line 29: static const int spd_array[] = { 0xA0, 0xA2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xA4, 0xA6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 14:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55224 ) Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55224/comment/fb2b881c_ed8c2bf4 PS1, Line 15: Also, as an example, transform hp/280_g2 to make use of this code. > nit: Probably mention that the Kconfig can be dropped once all relevant boards are updated to select […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 14:12:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Auto-configure SerialIoDevMode UPD
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Hello Felix Singer, Nico Huber, Furquan Shaikh, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55224 to look at the new patch set (#2). Change subject: soc/intel/skylake: Auto-configure SerialIoDevMode UPD ...................................................................... soc/intel/skylake: Auto-configure SerialIoDevMode UPD Introduce the `DERIVE_SERIALIO_CFG_FROM_DEV_STATE` Kconfig symbol, which allows omitting the `SerialIoDevMode` setting from devicetrees where the SerialIO settings can be derived from the PCI devices' state. Also, when the `INTEL_LPSS_UART_FOR_CONSOLE` option is selected, configure the UART specified by `UART_FOR_CONSOLE` to have FSP skip initialisation for it. Also, as an example, transform hp/280_g2 to make use of this code. Once all other boards have been updated, the newly-introduced Kconfig option can be removed. Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/Kconfig M src/mainboard/hp/280_g2/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c 4 files changed, 51 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/55224/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ec760e4dcc6b64e40c6ebd402642070f1de33a Gerrit-Change-Number: 55224 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55225 ) Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ...................................................................... Patch Set 1: (5 comments) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55225/comment/8462001c_7358d9b1 PS1, Line 95: memory > fill_mrc_memory_init_params()? I would drop the `memory_init_params` part because FSP-M is not just about memory init (although the biggest part of FSP-M is memory init). I would also use shorter names. So, how about using `fill_fspm_*_params()` for the function names? The `*` would be the name of each category, e.g. this function would be `fill_fspm_mrc_params()` or `fill_fspm_memory_params()`. https://review.coreboot.org/c/coreboot/+/55225/comment/d141c468_da656360 PS1, Line 187: static void disable_pcie_clksrc_memory_init_params(FSP_M_CONFIG *m_cfg, : const struct soc_intel_alderlake_config *config) : { : unsigned int i; : : for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { : if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) : m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; : else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) : m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; : else : m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; : m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; : } : } : : static void fill_pch_pcie_memory_init_params(FSP_M_CONFIG *m_cfg, : const struct soc_intel_alderlake_config *config) : { : m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); : pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, : CONFIG_MAX_PCH_ROOT_PORTS); : } : : static void fill_cpu_pcie_memory_init_params(FSP_M_CONFIG *m_cfg, : const struct soc_intel_alderlake_config *config) : { : m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); : pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, : CONFIG_MAX_CPU_ROOT_PORTS); : } I wouldn't create these three functions. Instead, just put this code inside `fill_pcie_rp_memory_init_params()` directly. https://review.coreboot.org/c/coreboot/+/55225/comment/084bd351_ed92d87d PS1, Line 219: static void fill_pcie_rp_memory_init_params(FSP_M_CONFIG *m_cfg, I'd place this function right below the definition of `pcie_rp_init` (near the top of this file). https://review.coreboot.org/c/coreboot/+/55225/comment/6728c0b1_a4770fc6 PS1, Line 235: /* Enable ISH controller */ Isn't what this comment says a biiiiit obvious? 😉 https://review.coreboot.org/c/coreboot/+/55225/comment/b8da8bcd_b0e986af PS1, Line 320: /* Fill IGD related FSP-M UPDs */ : fill_igd_memory_init_params(m_cfg, config); : : /* Fill Memory related FSP-M UPDs */ : fill_memory_memory_init_params(m_cfg, config); : : /* Fill CPU related FSP-M UPDs */ : fill_cpu_memory_init_params(m_cfg, config); : : /* Fill security related FSP-M UPDs */ : fill_security_memory_init_params(m_cfg); : : /* Fill UART debug related FSP-M UPDs */ : fill_uart_memory_init_params(m_cfg); : : /* Fill IPU related FSP-M UPDs */ : fill_ipu_memory_init_params(m_cfg); : : /* Fill SMBUS related FSP-M UPDs */ : fill_smbus_memory_init_params(m_cfg); : : /* Fill Miscellaneous FSP-M UPDs */ : fill_misc_memory_init_params(m_cfg, config); : : /* Fill Audio related FSP-M UPDs */ : fill_audio_memory_init_params(m_cfg, config); : : /* Fill PCIE related RP FSP-M UPDs */ : fill_pcie_rp_memory_init_params(m_cfg, config); : : /* Fill ISH related FSP-M UPD */ : fill_ish_memory_init_params(m_cfg); : : /* Fill TCSS related FSP-M UPD */ : fill_tcss_memory_init_params(m_cfg); : : /* Fill USB4/TBT related FSP-M UPD */ : fill_usb4_memory_init_params(m_cfg); : : /* Fill VT-d related FSP-M UPD */ : fill_vtd_memory_init_params(m_cfg); : : /* Fill trace related FSP-M UPD */ : fill_trace_memory_init_params(m_cfg); I don't think we need a comment on every function call. Another thing: if you update all functions to have the same signature (even if `config` is unused), we could turn this into a table: const void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) = { fill_igd_memory_init_params, fill_memory_memory_init_params, fill_cpu_memory_init_params, fill_security_memory_init_params, fill_uart_memory_init_params, fill_ipu_memory_init_params, fill_smbus_memory_init_params, fill_misc_memory_init_params, fill_audio_memory_init_params, fill_pcie_rp_memory_init_params, fill_ish_memory_init_params, fill_tcss_memory_init_params, fill_usb4_memory_init_params, fill_vtd_memory_init_params, fill_trace_memory_init_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params_list); i++) fill_fspm_params[i](m_cfg, config); However, just because we can do something doesn't mean we should. -- To view, visit https://review.coreboot.org/c/coreboot/+/55225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Gerrit-Change-Number: 55225 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 14:11:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn
by Maulik V Vaghela (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jamie Ryu, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak, Ronak Kanabar, Patrick Rudolph. Maulik V Vaghela has uploaded a new patch set (#6) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/54334 ) Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ...................................................................... soc/intel/alderlake: Add configurable value for UsbTcPortEn As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. BUG=b:184324979 TEST=Verified on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/54334/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/54334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd Gerrit-Change-Number: 54334 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Update Mainboard part number and Vendor
by Maulik V Vaghela (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath. Maulik V Vaghela has uploaded a new patch set (#9) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: mb/intel/adlrvp: Update Mainboard part number and Vendor ...................................................................... mb/intel/adlrvp: Update Mainboard part number and Vendor dmidecode output should match with the Kernel updated string. TEST=dmidecode grep "Manufacturer" = Intel Corporation dmidecode grep "Product name" = Alder Lake Client Platform Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/51408/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 9 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by Maulik V Vaghela (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Meera Ravindranath, Deepti Deshatty. Maulik V Vaghela has uploaded a new patch set (#7) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... mb/adlrvp: Fix DDR5 Boot issue Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2021