coreboot-gerrit June 2021

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Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55089 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz ...................................................................... mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz The I2C bus at which the external RTC is attached to is operated at standard speed (100 kHz) at coreboot runtime. The OS can choose to run it at fast speed since it uses its own driver and controller setup. Report additional bus timings for fast mode so that OS can do it right. Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55089 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 5 files changed, 35 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index b7590fa..20d44bb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -49,7 +49,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 160, .fall_time_ns = 110, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x58, + .scl_lcnt = 0xcf, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 336d6c4..06f4c05 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -47,7 +47,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 60, .fall_time_ns = 20, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x68, + .scl_lcnt = 0xd4, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 635ff3f..45cfd85 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -44,7 +44,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 40, .fall_time_ns = 10, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x68, + .scl_lcnt = 0xd1, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 48b4ad8..2500e08 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -47,7 +47,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 160, .fall_time_ns = 110, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x5b, + .scl_lcnt = 0xce, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index e2a3ea0..e058fde 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -18,7 +18,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 40, .fall_time_ns = 10, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x68, + .scl_lcnt = 0xd1, + .sda_hold = 0x28 + }, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/55089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Gerrit-Change-Number: 55089 Gerrit-PatchSet: 5 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... drivers/i2c/designware: Report I2C timings for additional bus speeds Since the OS provides its own driver for the I2C controller it can choose to use a bus speed other than the one used at coreboot runtime. In this case it would be good to provide a way how the needed bus timings are communicated to the OS, since these are very board-specific and there is no way that the OS can know them other than read the appropriate ACPI reported timings. This patch adds some code to report additional bus speed timings if there are some defined in the devicetree. Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 9 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 2e2d20d..a6498fb 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -803,7 +803,7 @@ struct dw_i2c_speed_config sgen; int bus; const char *path; - unsigned int speed; + unsigned int speed, i; bus = dw_i2c_soc_dev_to_bus(dev); @@ -826,12 +826,17 @@ /* Ensure a default speed is available */ speed = (bcfg->speed == 0) ? I2C_SPEED_FAST : bcfg->speed; - /* Report timing values for the OS driver */ + /* Report currently used timing values for the OS driver */ + acpigen_write_scope(path); if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) >= 0) { - acpigen_write_scope(path); dw_i2c_acpi_write_speed_config(&sgen); - acpigen_pop_len(); } + /* Now check if there are more speed settings available and report them as well. */ + for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) { + if (bcfg->speed_config[i].speed && speed != bcfg->speed_config[i].speed) + dw_i2c_acpi_write_speed_config(&bcfg->speed_config[i]); + } + acpigen_write_scope_end(); } static int dw_i2c_dev_transfer(struct device *dev, -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 5 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cret: Add new Goodix touchscreen
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54872 ) Change subject: mb/google/dedede/var/cret: Add new Goodix touchscreen ...................................................................... mb/google/dedede/var/cret: Add new Goodix touchscreen Add Goodix GT7996F touchscreen into devicetree for cret. BUG=b:180547935, b:188501391 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I2a6f7c1e9900492937202c0bc6595674f1e79e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/54872 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/cret/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 82002e4..9c2a73e 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -165,6 +165,24 @@ register "hid_desc_reg_offset" = "0x01" device i2c 16 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7996"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "100" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "300" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end end # I2C 2 device pci 15.3 off end # I2C 3 device pci 1c.7 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/54872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6f7c1e9900492937202c0bc6595674f1e79e5b Gerrit-Change-Number: 54872 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52090 ) Change subject: src/intel/xeon_sp: add hardware error support (HEST) ...................................................................... src/intel/xeon_sp: add hardware error support (HEST) This patch adds the ACPI hardware error source table (HEST) support. This involves a few different parts: (1) The ACPI HEST table which is filled with the appropriate fields (2) Reserved memory which is used by runtime SW to provide error information. OS will not accept a HEST table with this memory set to 0. The ASL code to enable APEI bit will be submitted in a separate patch. Tested on DeltaLake mainboard with following options enabled SOC_INTEL_XEON_RAS After boot to Linux, the following will show in dmesg: HEST: Table parsing has been initialized Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52090 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/include/soc/hest.h M src/soc/intel/xeon_sp/nb_acpi.c A src/soc/intel/xeon_sp/ras/Kconfig A src/soc/intel/xeon_sp/ras/Makefile.inc A src/soc/intel/xeon_sp/ras/hest.c 10 files changed, 179 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ae644de..84d0a31 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -6,6 +6,7 @@ #define CBMEM_ID_ACPI 0x41435049 #define CBMEM_ID_ACPI_BERT 0x42455254 #define CBMEM_ID_ACPI_GNVS 0x474e5653 +#define CMBMEM_ID_ACPI_HEST 0x48455354 #define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 @@ -81,6 +82,7 @@ { CBMEM_ID_ACPI, "ACPI " }, \ { CBMEM_ID_ACPI_BERT, "ACPI BERT " }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ + { CMBMEM_ID_ACPI_HEST, "ACPI HEST " }, \ { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 161381f..75215f8 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -24,4 +24,5 @@ UIOR, 8, // 0x2f - UART debug controller init on S3 resume A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource + , 8, // 0x40 - 0x48 Hest log buffer (used in SMM, not ASL code) } diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index c98fa01..89b682e 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -26,6 +26,7 @@ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ u64 a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */ u64 a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */ + u64 hest_log_addr; /* 0x40 - 48 err log addr (used in SMM, not ASL code) */ }; #endif diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 09f72a3..a2876b5 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -2,6 +2,7 @@ source "src/soc/intel/xeon_sp/skx/Kconfig" source "src/soc/intel/xeon_sp/cpx/Kconfig" +source "src/soc/intel/xeon_sp/ras/Kconfig" config XEON_SP_COMMON_BASE bool @@ -114,4 +115,9 @@ hex default 0x80000 +config SOC_INTEL_XEON_RAS + bool + select SOC_ACPI_HEST + select SOC_RAS_ELOG + endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 89e43fc..4c351a4 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -16,6 +16,8 @@ smm-y += smihandler.c pmutil.c postcar-y += spi.c +subdirs-$(CONFIG_SOC_INTEL_XEON_RAS) += ras + CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) diff --git a/src/soc/intel/xeon_sp/include/soc/hest.h b/src/soc/intel/xeon_sp/include/soc/hest.h new file mode 100644 index 0000000..ad79d45 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/hest.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _HEST_H_ +#define _HEST_H_ +#include <acpi/acpi.h> + +#define MCE_ERR_POLL_MS_INTERVAL 1000 +#define HEST_PCIE_RP_AER_DESC_TYPE 6 +#define HEST_GHES_DESC_TYPE 9 +#define GHES_MAX_RAW_DATA_LENGTH (((CONFIG_ERROR_LOG_BUFFER_SIZE) >> 1) - 8) +#define GHEST_ERROR_STATUS_BLOCK_LENGTH ((CONFIG_ERROR_LOG_BUFFER_SIZE) >> 1) +#define GHEST_ASSIST (1 << 2) +#define FIRMWARE_FIRST (1 << 0) +#define MEM_VALID_BITS 0x66ff +#define PCIE_VALID_BITS 0xef +#define QWORD_ACCESS 4 +#define NOTIFY_TYPE_SCI 3 + +/* Generic Error Source Descriptor */ +typedef struct acpi_ghes_esd { + u16 type; + u16 source_id; + u16 related_src_id; + u8 flags; + u8 enabled; + u32 prealloc_erecords; + u32 max_section_per_record; +} __packed acpi_ghes_esd_t; + +typedef struct ghes_record { + acpi_ghes_esd_t esd; + u32 max_raw_data_length; + acpi_addr64_t sts_addr; + acpi_hest_hen_t notify; + u32 err_sts_blk_len; +} __packed ghes_record_t; + +unsigned long hest_create(unsigned long current, struct acpi_rsdp *rsdp); + +#endif diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 19c3921..0c1c5ab 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <soc/acpi.h> #include <soc/cpu.h> +#include <soc/hest.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/soc_util.h> @@ -449,5 +450,8 @@ acpi_add_table(rsdp, dmar); } + if (CONFIG(SOC_ACPI_HEST)) + current = hest_create(current, rsdp); + return current; } diff --git a/src/soc/intel/xeon_sp/ras/Kconfig b/src/soc/intel/xeon_sp/ras/Kconfig new file mode 100644 index 0000000..79c599c --- /dev/null +++ b/src/soc/intel/xeon_sp/ras/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config SOC_ACPI_HEST + def_bool n + depends on HAVE_ACPI_TABLES + help + This variable provides control for ACPI hardware error source table (HEST) + +config SOC_RAS_ELOG + def_bool n + depends on SOC_ACPI_HEST + help + This variable provides enhanced error logging support used with HEST + +config ERROR_LOG_BUFFER_SIZE + hex + default 0x4000 + depends on SOC_RAS_ELOG + help + This variable allows a configurable error log based on system requirements diff --git a/src/soc/intel/xeon_sp/ras/Makefile.inc b/src/soc/intel/xeon_sp/ras/Makefile.inc new file mode 100644 index 0000000..93c8705 --- /dev/null +++ b/src/soc/intel/xeon_sp/ras/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SOC_ACPI_HEST) += hest.c diff --git a/src/soc/intel/xeon_sp/ras/hest.c b/src/soc/intel/xeon_sp/ras/hest.c new file mode 100644 index 0000000..6164edf --- /dev/null +++ b/src/soc/intel/xeon_sp/ras/hest.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <cbmem.h> +#include <console/console.h> +#include <soc/hest.h> +#include <intelblocks/nvs.h> + +static u64 hest_get_elog_addr(void) +{ + /* The elog address comes from reserved memory */ + struct global_nvs *gnvs; + gnvs = acpi_get_gnvs(); + if (!gnvs) { + printk(BIOS_ERR, "Unable to get gnvs\n"); + return 0; + } + + /* Runtime logging address */ + printk(BIOS_DEBUG, "\t status blk start addr = %llx\n", gnvs->hest_log_addr); + printk(BIOS_DEBUG, "\t size = %x\n", CONFIG_ERROR_LOG_BUFFER_SIZE); + return gnvs->hest_log_addr; +} + +static u32 acpi_hest_add_ghes(void *current) +{ + ghes_record_t *rec = (ghes_record_t *)current; + u32 size = sizeof(ghes_record_t); + + /* Fill GHES error source descriptor */ + memset(rec, 0, size); + rec->esd.type = HEST_GHES_DESC_TYPE; + rec->esd.source_id = 0; /* 0 for MCE check exception source */ + rec->esd.enabled = 1; + rec->esd.related_src_id = 0xffff; + rec->esd.prealloc_erecords = 1; + rec->esd.max_section_per_record = 0xf; + rec->max_raw_data_length = GHES_MAX_RAW_DATA_LENGTH; + + /* Add error_status_address */ + rec->sts_addr.space_id = 0; + rec->sts_addr.bit_width = 0x40; + rec->sts_addr.bit_offset = 0; + rec->sts_addr.access_size = QWORD_ACCESS; + + /* Add notification structure */ + rec->notify.type = NOTIFY_TYPE_SCI; + rec->notify.length = sizeof(acpi_hest_hen_t); + rec->err_sts_blk_len = GHEST_ERROR_STATUS_BLOCK_LENGTH; + + /* error status block entries start address */ + if (CONFIG(SOC_ACPI_HEST)) + rec->sts_addr.addr = hest_get_elog_addr(); + + return size; +} + +static unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + acpi_header_t *header = &(hest->header); + void *current; + current = (void *)(hest); + void *next = current; + next = hest + 1; + next += acpi_hest_add_ghes(next); + hest->error_source_count += 1; + header->length += next - current; + return header->length; +} + +unsigned long hest_create(unsigned long current, struct acpi_rsdp *rsdp) +{ + struct global_nvs *gnvs; + acpi_hest_t *hest; + + /* Reserve memory for Enhanced error logging */ + void *mem = cbmem_add(CMBMEM_ID_ACPI_HEST, CONFIG_ERROR_LOG_BUFFER_SIZE); + if (!mem) { + printk(BIOS_ERR, "Unable to allocate HEST memory\n"); + return current; + } + + printk(BIOS_DEBUG, "HEST memory created: %p\n", mem); + gnvs = acpi_get_gnvs(); + if (!gnvs) { + printk(BIOS_ERR, "Unable to get gnvs\n"); + return current; + } + gnvs->hest_log_addr = (uintptr_t)mem; + printk(BIOS_DEBUG, "elog_addr: %llx, size:%x\n", gnvs->hest_log_addr, + CONFIG_ERROR_LOG_BUFFER_SIZE); + + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, (void *)current); + current += hest->header.length; + return current; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 22 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add firmware configuration probing for audio
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54716 ) Change subject: mb/google/brya: Add firmware configuration probing for audio ...................................................................... mb/google/brya: Add firmware configuration probing for audio For all of the audio devices in overridetree.cb add the probe matches that will determine if the device should be enabled or not based on the selected audio daughter board type. AUDIO=MAX98357_ALC5682I_I2S: enable max98357, dmic1 and alc5682i AUDIO=MAX98373_ALC5682_SNDW: enable max98373, dmic2 and alc5682 BUG=b:188696010 TEST=test different audio devices based on fw_config value: > AUDIO=UNKNOWN ectool cbi set 6 0x00000000 4 2 > AUDIO=MAX98357_ALC5682I_I2S ectool cbi set 6 0x00000100 4 2 > AUDIO=MAX98373_ALC5682_SNDW ectool cbi set 6 0x00000200 4 2 Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54716 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/brya0/Makefile.inc A src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 4 files changed, 113 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 3acb07e..20999d6 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -7,6 +7,9 @@ select DRIVERS_I2C_SX9324 select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_SOUNDWIRE_ALC5682 + select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SPI_ACPI select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/brya/variants/brya0/Makefile.inc b/src/mainboard/google/brya/variants/brya0/Makefile.inc new file mode 100644 index 0000000..158c217 --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c new file mode 100644 index 0000000..66539af --- /dev/null +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +static const struct pad_config dmic_enable_pads[] = { + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ +}; + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +static const struct pad_config sndw_enable_pads[] = { + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), /* SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), /* SDW_SPKR_DATA */ +}; + +static const struct pad_config sndw_disable_pads[] = { + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), +}; + +static const struct pad_config i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */ +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NONE), + PAD_NC(GPP_R2, NONE), + PAD_NC(GPP_R3, NONE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) { + printk(BIOS_INFO, "Configure audio over SoundWire with MAX98373 ALC5682.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); + gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); + } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n"); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 6354c0d..2494fde 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -157,7 +157,9 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO MAX98357_ALC5682I_I2S + end end chip drivers/intel/mipi_camera register "acpi_hid" = ""OVTI8856"" @@ -401,7 +403,30 @@ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" register "sdmode_delay" = "5" - device generic 0 on end + device generic 0 on + probe AUDIO MAX98357_ALC5682I_I2S + end + end + + chip drivers/intel/soundwire + device generic 0 on + probe AUDIO MAX98373_ALC5682_SNDW + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 2.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 2.7 on end + end + end end end device ref gspi1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/54716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f159442516830f9d304d78c83f070e4fcff4a37 Gerrit-Change-Number: 54716 Gerrit-PatchSet: 9 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifier
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55028 ) Change subject: mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifier ...................................................................... mb/google/guybrush/var/guybrush: Reconfigure left speaker amplifier In order to resolve the I2C address conflict with another peripheral in the upcoming hardware build, left speaker amplifier I2C address is reconfigured. BUG=b:188539052 TEST=Build Guybrush mainboard. On Guybrush board ID 1, all the 3 speaker amplifiers are added to the ACPI table. \_SB.I2C2.D028: Realtek SPK AMP L at I2C: 03:28 \_SB.I2C2.D029: Realtek SPK AMP R at I2C: 03:29 \_SB.I2C2.D02A: Realtek SPK AMP L1 at I2C: 03:2a At the OS side, the concerned speaker amplifiers are probed and enumerated. localhost ~ # i2cdetect -y -r 2 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- UU -- -- -- -- -- 20: -- -- -- -- -- -- -- -- UU UU -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- Change-Id: I69a7e7dd65a459c2e5629ada1dea1f1660dd9990 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55028 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index fb8d9ca..97a1afd 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -132,6 +132,7 @@ register "hid" = ""10EC1019"" register "desc" = ""Realtek SPK AMP L"" register "uid" = "0" + register "probed" = "1" device i2c 28 on end end chip drivers/i2c/generic @@ -140,6 +141,13 @@ register "uid" = "1" device i2c 29 on end end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP L1"" + register "uid" = "2" + register "probed" = "1" + device i2c 2a on end + end end # I2C2 device ref uart_1 on -- To view, visit https://review.coreboot.org/c/coreboot/+/55028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69a7e7dd65a459c2e5629ada1dea1f1660dd9990 Gerrit-Change-Number: 55028 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec ...................................................................... mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (<400 kHz). Measured I2C frequency changes are just as below after tuning: touchpad: 434kHz ---> 391kHz touchpanel: 439kHz ---> 382kHz audio codec RT5682: 445kHz ---> 385kHz BUG=b:187555396 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400 kHz Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54249 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/blipper/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index df3f9dd..a5a7e48 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -21,18 +21,24 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 247, + .fall_time_ns = 11, }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 175, + .fall_time_ns = 20, }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 99, + .fall_time_ns = 7, }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 6 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/brya0: Fix irq and CS lines for FPMCU
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55147 ) Change subject: mb/google/brya/brya0: Fix irq and CS lines for FPMCU ...................................................................... mb/google/brya/brya0: Fix irq and CS lines for FPMCU The entries in the ACPI tables for the fingerprint module's SPI configuration were incorrect. 1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be described by Interrupt(), not GpioInt() 2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on` BUG=b:181635081 TEST=verified in kernel logs: localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi' [ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected [ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55147 Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 78fc472..6354c0d 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -410,9 +410,9 @@ register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F15)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" register "wake" = "GPE0_DW2_15" - device spi 1 on end + device spi 0 on end end # FPMCU end device ref pch_espi on -- To view, visit https://review.coreboot.org/c/coreboot/+/55147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d Gerrit-Change-Number: 55147 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block: Move mainboard api to tcss common block
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54733 ) Change subject: intel/common/block: Move mainboard api to tcss common block ...................................................................... intel/common/block: Move mainboard api to tcss common block As per the comments in CB:54090 mainboard api mainboard_tcss_get_port_info() is simplified and moved to tcss common block code. Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c M src/mainboard/google/volteer/mainboard.c M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 5 files changed, 58 insertions(+), 60 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/pmc_mux/conn/chip.h b/src/drivers/intel/pmc_mux/conn/chip.h index 8497350..461916e 100644 --- a/src/drivers/intel/pmc_mux/conn/chip.h +++ b/src/drivers/intel/pmc_mux/conn/chip.h @@ -23,4 +23,12 @@ enum typec_orientation hsl_orientation; }; +/* + * Method verifies input "conn" device. + * Returns 'true' if device passed is Intel PMC MUX Conn device else returns 'false'. + * Method also outputs the usb2 and usb3 port numbers associated with the 'conn' device + */ +bool intel_pmc_mux_conn_get_ports(const struct device *conn, unsigned int *usb2_port, + unsigned int *usb3_port); + #endif /* __DRIVERS_INTEL_PMC_MUX_CONN_H__ */ diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index 9fd8543..b6bf371 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -85,3 +85,18 @@ CHIP_NAME("Intel PMC MUX CONN Driver") .enable_dev = conn_enable, }; + +bool intel_pmc_mux_conn_get_ports(const struct device *conn, unsigned int *usb2_port, + unsigned int *usb3_port) +{ + const struct drivers_intel_pmc_mux_conn_config *mux_config; + + if (!conn->chip_info || conn->chip_ops != &drivers_intel_pmc_mux_conn_ops) + return false; + + mux_config = conn->chip_info; + *usb2_port = mux_config->usb2_port_number; + *usb3_port = mux_config->usb3_port_number; + + return true; +}; diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 5e52b01..7426445 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -142,63 +142,6 @@ } } -static bool is_correct_port(const struct device *dev, int port) -{ - return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == port - && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; -} - -static const struct drivers_intel_pmc_mux_conn_config *get_connector_config( - const struct device *mux, - int port) -{ - const struct drivers_intel_pmc_mux_conn_config *config = NULL; - DEVTREE_CONST struct device *conn = NULL; - - while ((conn = dev_bus_each_child(mux->link_list, conn)) != NULL) { - if (is_correct_port(conn, port)) - break; - } - - if (conn) - config = (const struct drivers_intel_pmc_mux_conn_config *) conn->chip_info; - - return config; -} - -const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports) -{ - static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; - size_t port; - const struct device *pmc; - const struct device *mux; - const struct drivers_intel_pmc_mux_conn_config *mux_config; - size_t active_ports = 0; - - pmc = pcidev_path_on_root(PCH_DEVFN_PMC); - if (!pmc || !pmc->link_list) { - printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); - return NULL; - } - - mux = pmc->link_list->children; - if (!mux) - return NULL; - - for (port = 0; port < MAX_TYPE_C_PORTS; port++) { - mux_config = get_connector_config(mux, port); - if (mux_config == NULL) - continue; - - port_map[active_ports].usb2_port = mux_config->usb2_port_number; - port_map[active_ports].usb3_port = mux_config->usb3_port_number; - active_ports++; - } - - *num_ports = active_ports; - return port_map; -} - static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 29093d1..9595a78 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -161,10 +161,10 @@ const struct tcss_mux_info *mainboard_tcss_get_mux_info(int port); /* - * Mainboard method to get only the port information to initialize the muxes to + * Method to get only the port information to initialize the muxes to * disconnect mode during boot. * returns tscc_port_map of all ports on system */ -const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports); +const struct tcss_port_map *tcss_get_port_info(size_t *num_ports); #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index da19954..28564e3 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -12,6 +12,7 @@ #include <soc/pcr_ids.h> #include <soc/tcss.h> #include <stdlib.h> +#include <drivers/intel/pmc_mux/conn/chip.h> #define BIAS_CTRL_VW_INDEX_SHIFT 16 #define BIAS_CTRL_BIT_POS_SHIFT 8 @@ -338,13 +339,44 @@ } } +const struct tcss_port_map *tcss_get_port_info(size_t *num_ports) +{ + static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; + size_t active_ports = 0; + size_t port; + + for (port = 0; port < MAX_TYPE_C_PORTS; port++) { + const struct device_path conn_path[] = { + {.type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_PMC}, + {.type = DEVICE_PATH_GENERIC, .generic.id = 0, .generic.subid = 0}, + {.type = DEVICE_PATH_GENERIC, .generic.id = port}, + }; + const struct device *conn = find_dev_nested_path(pci_root_bus(), conn_path, + ARRAY_SIZE(conn_path)); + unsigned int usb2_port, usb3_port; + + if (!conn) + continue; + + if (CONFIG(DRIVERS_INTEL_PMC) && + intel_pmc_mux_conn_get_ports(conn, &usb2_port, &usb3_port)) { + port_map[active_ports].usb2_port = usb2_port; + port_map[active_ports].usb3_port = usb3_port; + ++active_ports; + } + } + + *num_ports = active_ports; + return port_map; +} + void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PORTS]) { const struct tcss_port_map *port_map; size_t num_ports; size_t i; - port_map = mainboard_tcss_get_port_info(&num_ports); + port_map = tcss_get_port_info(&num_ports); if (port_map == NULL) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/54733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Gerrit-Change-Number: 54733 Gerrit-PatchSet: 9 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "util/vboot_lib: Add description.md"
by Patrick Georgi (Code Review) 04 Jun '21

04 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55162 ) Change subject: Revert "util/vboot_lib: Add description.md" ...................................................................... Revert "util/vboot_lib: Add description.md" This reverts commit 255b6f8646903594fb728f8228908792bad766f0. No longer needed after commit dd01e0131a8ba901bedec48844502fe85663390a (Revert "util/lint: Add test for documentation in util dirs") has been submitted. Plus, `util/vboot_lib/description.md` gets deleted whenever one runs `make -C util/cbfstool clean`, which is rather annoying. Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55162 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D util/vboot_lib/description.md 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/util/vboot_lib/description.md b/util/vboot_lib/description.md deleted file mode 100644 index d4c3a60..0000000 --- a/util/vboot_lib/description.md +++ /dev/null @@ -1 +0,0 @@ -Support library for vboot in cbfstool. -- To view, visit https://review.coreboot.org/c/coreboot/+/55162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4 Gerrit-Change-Number: 55162 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2021